Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

Simple Signal Generator

452 · Other digital · 1 × 2 tiles

by Matt Venn

Layout render of Simple Signal Generator

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		15k (19% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		27k (35% of buffer maximum)
Core covered by logic47%
Transistor density
transistors per mm²		270k average, 316k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Square wave generator with a phase-shifting second channel for metastability experiments

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_mattvenn_signal_generator
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 6, row 3 of the tile grid
Mux address452
LanguageVerilog
Clock50 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors31,174
Logic cells1,704 + 3,420 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

47%
46%
  • Logic cells 0.05 mm² (47%)
  • Filler and tap cells 0.05 mm² (46%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1732-input NAND gate
dffrnq_17t-5V 146D flip-flop with reset
clkinv_17t-5V 99Clock inverter
mux2_27t-5V 982-input multiplexer (2x drive)
xor2_17t-5V 902-input XOR gate
nor2_17t-5V 852-input NOR gate
oai21_17t-5V 75OR-AND-Invert compound gate
aoi21_17t-5V 52AND-OR-Invert compound gate
clkbuf_27t-5V 49Clock buffer (2x drive)
xor2_27t-5V 482-input XOR gate (2x drive)

Logic density map

23 logic cells, 2,122 transistors 128 logic cells, 2,589 transistors 152 logic cells, 2,663 transistors 65 logic cells, 1,078 transistors 59 logic cells, 2,361 transistors 236 logic cells, 3,265 transistors 240 logic cells, 3,172 transistors 91 logic cells, 1,323 transistors 58 logic cells, 2,362 transistors 228 logic cells, 3,339 transistors 216 logic cells, 3,399 transistors 78 logic cells, 1,388 transistors 5 logic cells, 459 transistors 46 logic cells, 621 transistors 62 logic cells, 735 transistors 17 logic cells, 298 transistors Densest SRAM-free 0.1 mm square: 269 logic cells 2k 13k 15k 6k 24k 24k 6k 23k 22k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (27k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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