Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

Tiny Pixel Processor

195 · RISC-V and CPUs · 2 × 2 tiles

by Julian Schlager, Thomas Lindinger, Patrick Pollak, Sebastian Gmeiner, Simon Vogelhuber

Layout render of Tiny Pixel Processor

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		21k (27% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		31k (41% of buffer maximum)
Core covered by logic64%
Transistor density
transistors per mm²		299k average, 316k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

A custom processor built for generating procedural graphics

Source repository Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_pixel_processor
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles2 × 2 at column 5, row 6 of the tile grid
Mux address195
LanguageVHDL
Clock50.35 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors70,145
Logic cells4,885 + 7,360 filler and tap cells
Libraries 7t-5V (5k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

64%
31%
  • Logic cells 0.15 mm² (64%)
  • Filler and tap cells 0.07 mm² (31%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffrnq_17t-5V 468D flip-flop with reset
mux2_27t-5V 3772-input multiplexer (2x drive)
nand2_17t-5V 3312-input NAND gate
buf_27t-5V 327Buffer (2x drive)
oai21_17t-5V 227OR-AND-Invert compound gate
nor2_17t-5V 2002-input NOR gate
aoi21_17t-5V 189AND-OR-Invert compound gate
clkbuf_27t-5V 176Clock buffer (2x drive)
buf_17t-5V 174Buffer
buf_47t-5V 164Buffer (4x drive)

Logic density map

178 logic cells, 3,146 transistors 236 logic cells, 3,167 transistors 195 logic cells, 3,140 transistors 214 logic cells, 3,056 transistors 231 logic cells, 2,877 transistors 215 logic cells, 2,880 transistors 248 logic cells, 2,946 transistors 12 logic cells, 209 transistors 202 logic cells, 3,388 transistors 236 logic cells, 3,448 transistors 183 logic cells, 3,146 transistors 264 logic cells, 3,353 transistors 283 logic cells, 3,328 transistors 284 logic cells, 3,103 transistors 278 logic cells, 3,162 transistors 20 logic cells, 225 transistors 180 logic cells, 3,218 transistors 190 logic cells, 3,299 transistors 178 logic cells, 3,076 transistors 226 logic cells, 2,977 transistors 235 logic cells, 2,896 transistors 192 logic cells, 2,846 transistors 210 logic cells, 3,035 transistors 15 logic cells, 202 transistors 15 logic cells, 536 transistors 34 logic cells, 647 transistors 44 logic cells, 687 transistors 47 logic cells, 603 transistors 38 logic cells, 562 transistors 2 logic cells, 478 transistors 0 logic cells, 476 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 310 logic cells 18k 24k 19k 21k 23k 21k 25k 20k 24k 18k 26k 28k 28k 28k 18k 19k 18k 23k 23k 19k 21k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (31k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

← 194 Tiny Tapeout Template Ayman All projects Julian_Proyecto 196 →