Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

Minimal RV32E SoC with UART Loader

103 · RISC-V and CPUs · 4 × 2 tiles

by Kris / KLuterIRV

Layout render of Minimal RV32E SoC with UART Loader

Rendered from the layout at 0.90 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		9k (12% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		34k (45% of buffer maximum)
Core covered by logic24%
Transistor density
transistors per mm²		161k average, 278k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Minimal RV32E microcontroller with UART program loader, internal instruction memory, GPIO and configurable 7-segment output

Source repository Its page on Tiny TapeoutBuy a chip and board

Size1440 × 325 µm (0.469 mm²)
Macrott_um_kluterirv_rv32e_core
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles4 × 2 at column 7, row 11 of the tile grid
Mux address103
LanguageVerilog
Clock20 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors76,559
Logic cells4,459 + 9,829 filler and tap cells
Libraries 7t-5V (4k)
SRAM2 macros, 2,048 bits

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells, fd SRAM
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, SRAM, filler and tap cells and other.

24%
49%
16%
11%
  • Logic cells 0.12 mm² (24%)
  • SRAM 0.23 mm² (49%)
  • Filler and tap cells 0.08 mm² (16%)
  • Other 0.05 mm² (11%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
oai21_17t-5V 510OR-AND-Invert compound gate
aoi21_17t-5V 460AND-OR-Invert compound gate
dffq_17t-5V 438D flip-flop (1 bit storage)
nand2_17t-5V 4042-input NAND gate
dlyb_17t-5V 348Delay buffer
clkbuf_27t-5V 208Clock buffer (2x drive)
aoi22_17t-5V 180AND-OR-Invert (2x2 inputs)
nor2_17t-5V 1732-input NOR gate
clkinv_17t-5V 162Clock inverter
buf_17t-5V 158Buffer

Logic density map

0 logic cells, 792 transistors, 68% SRAM 0 logic cells, 533 transistors, 72% SRAM 6 logic cells, 445 transistors, 72% SRAM 18 logic cells, 880 transistors, 72% SRAM 163 logic cells, 1,704 transistors, 26% SRAM 252 logic cells, 2,787 transistors 277 logic cells, 2,883 transistors 267 logic cells, 2,683 transistors 262 logic cells, 2,593 transistors 130 logic cells, 2,170 transistors, 4% SRAM 5 logic cells, 875 transistors, 72% SRAM 1 logic cells, 494 transistors, 72% SRAM 1 logic cells, 395 transistors, 72% SRAM 0 logic cells, 878 transistors, 72% SRAM 0 logic cells, 172 transistors, 48% SRAM 0 logic cells, 511 transistors, 95% SRAM 0 logic cells, 334 transistors, 100% SRAM 0 logic cells, 315 transistors, 100% SRAM 0 logic cells, 535 transistors, 100% SRAM 132 logic cells, 1,689 transistors, 37% SRAM 279 logic cells, 2,947 transistors 243 logic cells, 3,201 transistors 318 logic cells, 2,838 transistors 297 logic cells, 2,737 transistors 205 logic cells, 2,395 transistors, 5% SRAM 0 logic cells, 594 transistors, 100% SRAM 0 logic cells, 285 transistors, 100% SRAM 0 logic cells, 281 transistors, 100% SRAM 0 logic cells, 608 transistors, 100% SRAM 0 logic cells, 73 transistors, 67% SRAM 0 logic cells, 2,673 transistors, 92% SRAM 0 logic cells, 1,139 transistors, 97% SRAM 0 logic cells, 298 transistors, 97% SRAM 0 logic cells, 2,855 transistors, 97% SRAM 122 logic cells, 2,331 transistors, 36% SRAM 275 logic cells, 2,872 transistors 233 logic cells, 3,172 transistors 238 logic cells, 2,965 transistors 258 logic cells, 2,934 transistors 147 logic cells, 2,303 transistors, 5% SRAM 0 logic cells, 3,055 transistors, 97% SRAM 0 logic cells, 807 transistors, 97% SRAM 0 logic cells, 266 transistors, 97% SRAM 0 logic cells, 3,201 transistors, 97% SRAM 0 logic cells, 489 transistors, 64% SRAM 0 logic cells, 236 transistors 2 logic cells, 256 transistors 26 logic cells, 323 transistors 28 logic cells, 340 transistors 45 logic cells, 454 transistors 56 logic cells, 595 transistors 66 logic cells, 625 transistors 43 logic cells, 582 transistors 60 logic cells, 606 transistors 4 logic cells, 445 transistors 0 logic cells, 260 transistors 0 logic cells, 254 transistors 0 logic cells, 250 transistors 0 logic cells, 254 transistors 0 logic cells, 92 transistors gf180mcu_fd_ip_sram__sram128x8m8wm1 gf180mcu_fd_ip_sram__sram128x8m8wm1 Densest SRAM-free 0.1 mm square: 341 logic cells 0 0 1k 2k 16k 25k 28k 27k 26k 13k <1k <1k <1k 0 0 0 0 0 13k 28k 24k 32k 30k 20k 0 0 0 0 0 0 0 0 12k 27k 23k 24k 26k 15k 0 0 0 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (34k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_fd_ip_sram__sram128x8m8wm12 1,024

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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