Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

teenytpu

384 · Accelerators · 1 × 2 tiles

by joannec34

Layout render of teenytpu

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		23k (31% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		37k (49% of buffer maximum)
Core covered by logic61%
Transistor density
transistors per mm²		284k average, 330k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

2x2 INT8 systolic-array TPU with SPI memory interface

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_joannec34_teenytpu
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 3, row 3 of the tile grid
Mux address384
LanguageVerilog
Clock50 MHz
Built withLibreLane 3.0.0, open_pdks 54435919abff
Transistors32,817
Logic cells2,687 + 3,047 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

61%
33%
  • Logic cells 0.07 mm² (61%)
  • Filler and tap cells 0.04 mm² (33%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 5362-input NAND gate
nor2_17t-5V 2082-input NOR gate
xor2_17t-5V 1952-input XOR gate
oai21_17t-5V 192OR-AND-Invert compound gate
dffrnq_17t-5V 152D flip-flop with reset
aoi21_17t-5V 125AND-OR-Invert compound gate
clkinv_17t-5V 111Clock inverter
xnor2_17t-5V 882-input XNOR gate
xor3_17t-5V 743-input XOR gate
aoi22_17t-5V 69AND-OR-Invert (2x2 inputs)

Logic density map

84 logic cells, 2,213 transistors 205 logic cells, 2,697 transistors 267 logic cells, 2,757 transistors 59 logic cells, 1,070 transistors 149 logic cells, 2,631 transistors 271 logic cells, 3,553 transistors 320 logic cells, 3,433 transistors 119 logic cells, 1,398 transistors 302 logic cells, 2,962 transistors 308 logic cells, 3,391 transistors 326 logic cells, 3,349 transistors 113 logic cells, 1,298 transistors 10 logic cells, 470 transistors 73 logic cells, 641 transistors 62 logic cells, 667 transistors 19 logic cells, 287 transistors Densest SRAM-free 0.1 mm square: 370 logic cells 8k 20k 27k 15k 27k 32k 30k 31k 33k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (37k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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