Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

GPS_Accelerator

390 · Accelerators · 1 × 2 tiles

by jpigdon

Layout render of GPS_Accelerator

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		30k (39% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		37k (49% of buffer maximum)
Core covered by logic81%
Transistor density
transistors per mm²		306k average, 337k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

GNSS Accelerator to demonstrate acquisition and tracking on Tiny Tapeout

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_jpigdon_gps_accelerator_top
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 0, row 3 of the tile grid
Mux address390
LanguageVHDL
Clock2.2 MHz
Built withLibreLane 3.0.0, open_pdks 54435919abff
Transistors35,372
Logic cells3,457 + 2,818 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

81%
13%
  • Logic cells 0.09 mm² (81%)
  • Filler and tap cells 0.01 mm² (13%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 5572-input NAND gate
oai21_17t-5V 417OR-AND-Invert compound gate
dffq_17t-5V 229D flip-flop (1 bit storage)
dffrnq_17t-5V 219D flip-flop with reset
nor2_17t-5V 2112-input NOR gate
aoi21_17t-5V 209AND-OR-Invert compound gate
dlyb_17t-5V 207Delay buffer
clkinv_17t-5V 190Clock inverter
xor2_17t-5V 1722-input XOR gate
nand3_17t-5V 1563-input NAND gate

Logic density map

297 logic cells, 2,908 transistors 322 logic cells, 3,076 transistors 334 logic cells, 3,124 transistors 143 logic cells, 1,289 transistors 328 logic cells, 3,101 transistors 326 logic cells, 3,290 transistors 314 logic cells, 3,254 transistors 144 logic cells, 1,378 transistors 281 logic cells, 3,237 transistors 257 logic cells, 3,480 transistors 308 logic cells, 3,408 transistors 145 logic cells, 1,362 transistors 85 logic cells, 683 transistors 62 logic cells, 744 transistors 81 logic cells, 735 transistors 30 logic cells, 303 transistors Densest SRAM-free 0.1 mm square: 372 logic cells 30k 32k 33k 33k 33k 31k 28k 26k 31k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (37k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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