Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

Tiny TPU Systolic Array

388 · Accelerators · 1 × 2 tiles

by Yu Xia，Bohong Gao, Junjie Yan, Yufeng Wang, Jinyao Sun, Arthur Stanson

Layout render of Tiny TPU Systolic Array

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		13k (17% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		28k (37% of buffer maximum)
Core covered by logic41%
Transistor density
transistors per mm²		259k average, 316k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

A small systolic-array-based matrix multiplication accelerator

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_bgao43
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 1, row 3 of the tile grid
Mux address388
LanguageSystemVerilog
Clock100 MHz
Built withLibreLane 3.0.0, open_pdks 54435919abff
Transistors29,952
Logic cells1,529 + 3,351 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

41%
53%
  • Logic cells 0.05 mm² (41%)
  • Filler and tap cells 0.06 mm² (53%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1852-input NAND gate
dffrnq_17t-5V 146D flip-flop with reset
nor2_17t-5V 892-input NOR gate
clkinv_17t-5V 86Clock inverter
oai21_17t-5V 82OR-AND-Invert compound gate
aoi21_17t-5V 77AND-OR-Invert compound gate
clkbuf_27t-5V 58Clock buffer (2x drive)
mux2_27t-5V 562-input multiplexer (2x drive)
xor2_17t-5V 482-input XOR gate
dlyb_17t-5V 47Delay buffer

Logic density map

2 logic cells, 2,031 transistors 62 logic cells, 2,328 transistors 89 logic cells, 2,332 transistors 7 logic cells, 920 transistors 67 logic cells, 2,331 transistors 261 logic cells, 3,488 transistors 251 logic cells, 3,248 transistors 73 logic cells, 1,384 transistors 85 logic cells, 2,347 transistors 237 logic cells, 3,187 transistors 245 logic cells, 3,064 transistors 52 logic cells, 1,266 transistors 1 logic cells, 448 transistors 35 logic cells, 611 transistors 44 logic cells, 670 transistors 18 logic cells, 297 transistors Densest SRAM-free 0.1 mm square: 283 logic cells <1k 6k 9k 7k 26k 25k 8k 24k 24k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (28k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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