Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

RHD2164-MCU-SPI Bridge

356 · Other digital · 1 × 2 tiles

by Manuel Monge

Layout render of RHD2164-MCU-SPI Bridge

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		24k (32% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		32k (42% of buffer maximum)
Core covered by logic83%
Transistor density
transistors per mm²		322k average, 342k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Various SPIs

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_top
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 6, row 14 of the tile grid
Mux address356
LanguageVerilog
Clock25 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors37,171
Logic cells2,793 + 2,434 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

83%
10%
  • Logic cells 0.10 mm² (83%)
  • Filler and tap cells 0.01 mm² (10%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
mux2_27t-5V 4402-input multiplexer (2x drive)
dffrnq_17t-5V 376D flip-flop with reset
dffq_17t-5V 256D flip-flop (1 bit storage)
dlyb_17t-5V 217Delay buffer
nand2_17t-5V 1852-input NAND gate
aoi22_17t-5V 183AND-OR-Invert (2x2 inputs)
clkbuf_27t-5V 148Clock buffer (2x drive)
clkinv_17t-5V 99Clock inverter
oai21_17t-5V 96OR-AND-Invert compound gate
clkbuf_17t-5V 95Clock buffer

Logic density map

200 logic cells, 3,299 transistors 244 logic cells, 3,361 transistors 265 logic cells, 3,455 transistors 112 logic cells, 1,452 transistors 234 logic cells, 3,278 transistors 233 logic cells, 3,448 transistors 284 logic cells, 3,450 transistors 111 logic cells, 1,467 transistors 271 logic cells, 3,159 transistors 271 logic cells, 3,394 transistors 267 logic cells, 3,475 transistors 97 logic cells, 1,479 transistors 63 logic cells, 664 transistors 63 logic cells, 741 transistors 56 logic cells, 730 transistors 22 logic cells, 319 transistors Densest SRAM-free 0.1 mm square: 318 logic cells 20k 24k 26k 23k 23k 28k 27k 27k 27k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (32k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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