Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

APA102 to WS2812 Translator

448 · Other digital · 1 × 2 tiles

by Squidgeefish

Layout render of APA102 to WS2812 Translator

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		16k (22% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		33k (44% of buffer maximum)
Core covered by logic42%
Transistor density
transistors per mm²		256k average, 329k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Convert a 7-LED APA102 stream to a WS2812-compatible one

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_apa102_ws2812_squidgeefish
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 4, row 3 of the tile grid
Mux address448
LanguageVerilog
Clock25 MHz
Built withLibreLane 3.0.0, open_pdks 54435919abff
Transistors29,567
Logic cells1,899 + 3,793 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

42%
51%
  • Logic cells 0.05 mm² (42%)
  • Filler and tap cells 0.06 mm² (51%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 216D flip-flop (1 bit storage)
aoi21_17t-5V 205AND-OR-Invert compound gate
nor2_17t-5V 1912-input NOR gate
nand3_17t-5V 1473-input NAND gate
nand2_17t-5V 1442-input NAND gate
aoi22_17t-5V 101AND-OR-Invert (2x2 inputs)
buf_27t-5V 84Buffer (2x drive)
buf_17t-5V 78Buffer
dlyb_17t-5V 72Delay buffer
clkbuf_27t-5V 60Clock buffer (2x drive)

Logic density map

22 logic cells, 2,098 transistors 169 logic cells, 2,586 transistors 196 logic cells, 2,677 transistors 48 logic cells, 1,021 transistors 49 logic cells, 2,269 transistors 313 logic cells, 3,101 transistors 316 logic cells, 3,357 transistors 107 logic cells, 1,253 transistors 29 logic cells, 2,203 transistors 232 logic cells, 2,963 transistors 246 logic cells, 3,067 transistors 81 logic cells, 1,211 transistors 0 logic cells, 446 transistors 42 logic cells, 513 transistors 41 logic cells, 582 transistors 8 logic cells, 220 transistors Densest SRAM-free 0.1 mm square: 333 logic cells 2k 17k 20k 5k 31k 32k 3k 23k 25k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (33k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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