Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2
Gen1 Digital Companion Tile
192 · Other digital · 1 × 1 tile
by Juan Fernandez · repository @JuanCarlosFdezMlg
Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
224 logic cells: too few for density figures, which are given for projects of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
Symbolic pulse-update and write-verify companion tile for a future local memristive AI chip
Source repository no longer public Its page on Tiny TapeoutBuy a chip and board
| Size | 347 × 161 µm (0.056 mm²) |
|---|---|
| Macro | tt_um_gen1_digital_companion_tile |
| Files | documentation · licence · layout and netlist in Tiny Tapeout GF 26a |
| Tiles | 1 × 1 at column 4, row 7 of the tile grid |
| Mux address | 192 |
| Language | Verilog |
| Clock | 20 MHz |
| Built with | LibreLane 3.0.3, open_pdks 54435919abff |
| Transistors | 12,180 |
| Logic cells | 224 + 1,332 filler and tap cells |
| Libraries | 7t-5V (224) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Where the area went
How this project's area splits between logic cells, filler and tap cells and other.
- Logic cells 0.01 mm² (12%)
- Filler and tap cells 0.05 mm² (81%)
- Other 4,033 µm² (7%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| nor2_1 | 7t-5V | 26 | 2-input NOR gate |
| dffrnq_1 | 7t-5V | 25 | D flip-flop with reset |
| clkinv_1 | 7t-5V | 20 | Clock inverter |
| nand2_1 | 7t-5V | 18 | 2-input NAND gate |
| dlyb_1 | 7t-5V | 15 | Delay buffer |
| aoi21_1 | 7t-5V | 11 | AND-OR-Invert compound gate |
| buf_2 | 7t-5V | 9 | Buffer (2x drive) |
| oai21_1 | 7t-5V | 9 | OR-AND-Invert compound gate |
| aoi22_1 | 7t-5V | 7 | AND-OR-Invert (2x2 inputs) |
| clkbuf_2 | 7t-5V | 7 | Clock buffer (2x drive) |
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.