Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

serv_soc_wb

135 · RISC-V and CPUs · 3 × 2 tiles

by Juan David Guerrero Balaguera

Layout render of serv_soc_wb

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		28k (37% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		36k (47% of buffer maximum)
Core covered by logic81%
Transistor density
transistors per mm²		315k average, 324k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Custom SOC using the SERV processor under RV32e

Source repository Its page on Tiny TapeoutBuy a chip and board

Size1076 × 325 µm (0.350 mm²)
Macrott_um_divadnauj_GB_serv_soc_wb
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles3 × 2 at column 0, row 6 of the tile grid
Mux address135
LanguageVerilog
Clock25 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors112,309
Logic cells9,987 + 9,349 filler and tap cells
Libraries 7t-5V (10k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

81%
14%
  • Logic cells 0.29 mm² (81%)
  • Filler and tap cells 0.05 mm² (14%)
  • Other 0.02 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1,5032-input NAND gate
dffq_17t-5V 1,017D flip-flop (1 bit storage)
inv_17t-5V 713Inverter
dffrnq_17t-5V 684D flip-flop with reset
oai21_27t-5V 656OR-AND-Invert compound gate (2x drive)
buf_27t-5V 585Buffer (2x drive)
mux2_27t-5V 5412-input multiplexer (2x drive)
buf_17t-5V 487Buffer
nor2_17t-5V 3942-input NOR gate
oai21_17t-5V 323OR-AND-Invert compound gate

Logic density map

238 logic cells, 3,214 transistors 288 logic cells, 3,175 transistors 316 logic cells, 3,135 transistors 308 logic cells, 3,143 transistors 258 logic cells, 3,284 transistors 229 logic cells, 3,352 transistors 271 logic cells, 3,309 transistors 307 logic cells, 3,198 transistors 295 logic cells, 3,172 transistors 283 logic cells, 3,168 transistors 188 logic cells, 2,171 transistors 275 logic cells, 3,204 transistors 287 logic cells, 3,193 transistors 304 logic cells, 3,304 transistors 283 logic cells, 3,332 transistors 277 logic cells, 3,240 transistors 287 logic cells, 3,321 transistors 323 logic cells, 3,253 transistors 317 logic cells, 3,323 transistors 301 logic cells, 3,292 transistors 293 logic cells, 3,311 transistors 197 logic cells, 2,324 transistors 276 logic cells, 3,166 transistors 284 logic cells, 3,332 transistors 295 logic cells, 3,292 transistors 333 logic cells, 3,207 transistors 280 logic cells, 3,302 transistors 292 logic cells, 3,203 transistors 272 logic cells, 3,251 transistors 290 logic cells, 3,375 transistors 298 logic cells, 3,398 transistors 306 logic cells, 3,309 transistors 198 logic cells, 2,377 transistors 63 logic cells, 711 transistors 57 logic cells, 792 transistors 60 logic cells, 749 transistors 70 logic cells, 702 transistors 75 logic cells, 696 transistors 74 logic cells, 669 transistors 84 logic cells, 684 transistors 76 logic cells, 689 transistors 68 logic cells, 730 transistors 67 logic cells, 729 transistors 44 logic cells, 528 transistors Densest SRAM-free 0.1 mm square: 360 logic cells 24k 29k 32k 31k 26k 23k 27k 31k 29k 28k 19k 27k 29k 30k 28k 28k 29k 32k 32k 30k 29k 20k 28k 28k 29k 33k 28k 29k 27k 29k 30k 31k 20k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (36k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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