Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

Simple MAC Engine w/ Postproc

450 · Other digital · 1 × 2 tiles

by Luca Goddijn

Layout render of Simple MAC Engine w/ Postproc

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		23k (30% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		28k (38% of buffer maximum)
Core covered by logic65%
Transistor density
transistors per mm²		291k average, 310k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Quantized INT8 MAC engine with bias, activation, and quantizer postproc, SPI-controlled

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_arty3_mac_engine
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 5, row 3 of the tile grid
Mux address450
LanguageSystemVerilog
Clock25 MHz
Built withLibreLane 3.0.0, open_pdks 54435919abff
Transistors33,555
Logic cells2,601 + 3,930 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

65%
28%
  • Logic cells 0.08 mm² (65%)
  • Filler and tap cells 0.03 mm² (28%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 3582-input NAND gate
dffrnq_17t-5V 276D flip-flop with reset
nor2_17t-5V 1642-input NOR gate
oai21_17t-5V 152OR-AND-Invert compound gate
dlyb_17t-5V 143Delay buffer
mux2_27t-5V 1292-input multiplexer (2x drive)
clkinv_17t-5V 117Clock inverter
xor2_17t-5V 1042-input XOR gate
buf_27t-5V 101Buffer (2x drive)
aoi21_17t-5V 91AND-OR-Invert compound gate

Logic density map

224 logic cells, 2,894 transistors 236 logic cells, 2,813 transistors 231 logic cells, 2,972 transistors 115 logic cells, 1,173 transistors 236 logic cells, 2,803 transistors 248 logic cells, 2,980 transistors 262 logic cells, 3,174 transistors 111 logic cells, 1,334 transistors 235 logic cells, 2,853 transistors 224 logic cells, 3,417 transistors 234 logic cells, 3,512 transistors 88 logic cells, 1,367 transistors 40 logic cells, 606 transistors 53 logic cells, 677 transistors 41 logic cells, 690 transistors 23 logic cells, 290 transistors Densest SRAM-free 0.1 mm square: 285 logic cells 22k 24k 23k 24k 25k 26k 23k 22k 23k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (28k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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