Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

Very Low Resource Digital Implementation of Bioimpedance Analysis

199 · Other digital · 2 × 2 tiles

by Fabien

Layout render of Very Low Resource Digital Implementation of Bioimpedance Analysis

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		12k (16% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		23k (30% of buffer maximum)
Core covered by logic39%
Transistor density
transistors per mm²		258k average, 304k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Digital bioimpedance demodulator with 8-stage I/Q cascade and UART output

Source repository Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_bioimpedance
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles2 × 2 at column 7, row 6 of the tile grid
Mux address199
LanguageVerilog
Clock1 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors60,553
Logic cells2,825 + 6,993 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

39%
57%
  • Logic cells 0.09 mm² (39%)
  • Filler and tap cells 0.13 mm² (57%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffrnq_17t-5V 515D flip-flop with reset
nor2_17t-5V 3852-input NOR gate
dlyb_17t-5V 177Delay buffer
oai21_17t-5V 159OR-AND-Invert compound gate
nand2_17t-5V 1452-input NAND gate
mux2_27t-5V 1392-input multiplexer (2x drive)
xor2_17t-5V 1352-input XOR gate
xnor2_17t-5V 1142-input XNOR gate
clkbuf_27t-5V 92Clock buffer (2x drive)
clkbuf_17t-5V 89Clock buffer

Logic density map

46 logic cells, 2,189 transistors 134 logic cells, 2,580 transistors 184 logic cells, 2,817 transistors 196 logic cells, 2,833 transistors 130 logic cells, 2,569 transistors 0 logic cells, 2,128 transistors 0 logic cells, 2,129 transistors 0 logic cells, 147 transistors 147 logic cells, 2,623 transistors 214 logic cells, 3,095 transistors 206 logic cells, 3,121 transistors 202 logic cells, 3,149 transistors 188 logic cells, 2,913 transistors 0 logic cells, 2,204 transistors 0 logic cells, 2,219 transistors 0 logic cells, 153 transistors 162 logic cells, 2,679 transistors 210 logic cells, 3,104 transistors 207 logic cells, 3,157 transistors 198 logic cells, 3,117 transistors 184 logic cells, 2,960 transistors 0 logic cells, 2,205 transistors 0 logic cells, 2,218 transistors 0 logic cells, 153 transistors 30 logic cells, 544 transistors 55 logic cells, 693 transistors 49 logic cells, 656 transistors 47 logic cells, 637 transistors 36 logic cells, 579 transistors 0 logic cells, 473 transistors 0 logic cells, 476 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 231 logic cells 5k 13k 18k 20k 13k 0 0 15k 21k 21k 20k 19k 0 0 16k 21k 21k 20k 18k 0 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (23k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

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