Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

Tensor Processing Unit For GF

454 · Other digital · 1 × 2 tiles

by Mocus Zhang

Layout render of Tensor Processing Unit For GF

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		25k (34% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		30k (40% of buffer maximum)
Core covered by logic70%
Transistor density
transistors per mm²		299k average, 329k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

multiplies fp8 matrices

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_tpu
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 7, row 3 of the tile grid
Mux address454
LanguageVerilog
Clock30 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors34,529
Logic cells2,941 + 3,701 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

70%
23%
  • Logic cells 0.08 mm² (70%)
  • Filler and tap cells 0.03 mm² (23%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 3412-input NAND gate
clkinv_17t-5V 219Clock inverter
nor2_17t-5V 2032-input NOR gate
dffq_17t-5V 175D flip-flop (1 bit storage)
oai21_17t-5V 175OR-AND-Invert compound gate
xor2_17t-5V 1372-input XOR gate
aoi21_17t-5V 122AND-OR-Invert compound gate
and2_17t-5V 852-input AND gate
aoi22_17t-5V 78AND-OR-Invert (2x2 inputs)
nand3_17t-5V 733-input NAND gate

Logic density map

227 logic cells, 2,641 transistors 266 logic cells, 3,031 transistors 275 logic cells, 3,070 transistors 112 logic cells, 1,240 transistors 270 logic cells, 2,967 transistors 279 logic cells, 3,275 transistors 273 logic cells, 3,375 transistors 125 logic cells, 1,429 transistors 255 logic cells, 2,953 transistors 258 logic cells, 3,423 transistors 273 logic cells, 3,390 transistors 108 logic cells, 1,501 transistors 51 logic cells, 611 transistors 67 logic cells, 647 transistors 73 logic cells, 680 transistors 29 logic cells, 296 transistors Densest SRAM-free 0.1 mm square: 302 logic cells 23k 27k 27k 27k 28k 27k 25k 26k 27k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (30k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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