wafer.space Run 2

Flip Chip pad test version 1

FC01 · Test structures · ½ × ½ slot

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Just some test pads for flip chip bonding trials

Die1.94 × 2.53 mm (4.9 mm²)
Core area1.74 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring4.68 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot G2 FC01 on the reticle
Bond pads12
Transistors0
Logic cells0
SRAMNo SRAM

Submission

LicenceApache-2.0 declared
No public repository
Chip-on-boardNot selected at submission
PrecheckNo finished precheck recorded

Where the area went

How this design's area splits between other and pad ring.

35%
65%
  • Other 1.74 mm² (35%)
  • Pad ring 3.17 mm² (65%)

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.