wafer.space Run 2

Test chip with 3.3V SRAM blocks using regular design rules

FS01 · Memory test chip · ½ × 1 slot

Layout render of Test chip with 3.3V SRAM blocks using regular design rules

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		1k (1% of buffer maximum)
over the 4.47 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		<1k
over all 9.57 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		2k (2% of buffer maximum)
Core covered by logic2%
Transistor density
transistors per mm²		271k average, 233k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Source repository

Die1.94 × 5.12 mm (9.9 mm²)
Core area4.47 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring9.57 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot H5 FS01 on the reticle
Bond pads72
Transistors1,211,472
Logic cells3,540 + 87,332 filler and tap cells
Libraries 7t-5V (4k)
SRAMNo SRAM

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 (in source file headers) — agrees
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 2ce18dbe27df.
Chip-on-boardSelected at submission
PrecheckPassed the check it was accepted on, 2026-07-15, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 V323,352 custom transistors
5 V7t-5V standard cells
Gate oxidesThin (3.3 V) and thick (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (850 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and pad ring.

38%
55%
  • Logic cells 0.07 mm² (1%)
  • Filler and tap cells 3.75 mm² (38%)
  • Other 0.65 mm² (7%)
  • Pad ring 5.46 mm² (55%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
buf_27t-5V 1,176Buffer (2x drive)
buf_47t-5V 1,027Buffer (4x drive)
buf_17t-5V 833Buffer
clkbuf_17t-5V 292Clock buffer
aoi22_17t-5V 69AND-OR-Invert (2x2 inputs)
dffq_17t-5V 38D flip-flop (1 bit storage)
dffq_27t-5V 23D flip-flop (1 bit storage, 2x drive)
clkbuf_27t-5V 22Clock buffer (2x drive)
nand3_27t-5V 103-input NAND gate (2x drive)
and4_17t-5V 84-input AND gate

Logic density map

30 logic cells, 72,519 transistors 19 logic cells, 64,807 transistors 130 logic cells, 160,574 transistors 460 logic cells, 130,764 transistors 151 logic cells, 150,430 transistors 1,434 logic cells, 134,209 transistors 306 logic cells, 153,018 transistors 921 logic cells, 161,958 transistors 51 logic cells, 93,050 transistors 38 logic cells, 89,840 transistors 0 logic cells, 156 transistors 0 logic cells, 147 transistors Densest SRAM-free mm²: 1,845 logic cells <1k <1k <1k <1k <1k 1k <1k 1k <1k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (2k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. FS01 was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-15.

Every step, and the latest re-run
StepAccepted on
check 665, 2026-07-15, initial, gf180mcu-precheck 1.7.2 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 778, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.CheckPadMaskpassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCadvisory warningadvisory warning
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)1,1681,168
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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