Tiny Tapeout GF 26bDie T26B on wafer.space Run 2

90 projects on one chip, measured one by one and as a whole die

Buy a chip and board Put your design on the next one All its projects on tinytapeout.com

What was built

The chip as a whole: what its projects add up to.

90

Projects

on the chip

86

Open source

with a public repository

2.5M

Transistors

across the unique designs

149k

Logic cells

gates and flip-flops

Counted inside the projects only, so these totals are smaller than the die's own figures on its run's page: the pads, Tiny Tapeout's multiplexer and controller and the fill are left out.

Get this chip, or make your own

Tiny Tapeout puts many small designs on one chip. Start with a tile, then come back with a whole die.

Get a Tiny Tapeout chip

Every Tiny Tapeout chip comes on a board you can plug in, with all of its projects ready to try.

Buy a chip and board

Put your design on the next one

Tiny Tapeout GF 26c and 26d take projects until 7 December 2026, to be made on wafer.space Run 3.

Submit a project

Make a whole chip of your own

When a design outgrows a few tiles, it can have a die to itself on wafer.space Run 3: orders close 9 December 2026.

Reserve a slot

The die

519 518 391 390 135 134 007 038 039 295 551 517 516 389 132 005 036 549 515 514 387 386 130 003 034 547 513 512 385 129 128 001 000 032 033 288 545 577 576 449 192 065 096 352 353 480 481 608 609 579 578 451 450 195 194 067 098 354 355 482 483 610 611 581 580 453 196 069 100 101 356 357 484 485 612 613 583 582 455 454 199 198 071 102 103 358 359 486 487 614

Every design rendered from the layout at the same scale and placed where it sits on the 3.9 × 5.1 mm die. Point at a project to see its name, and select it for its details.Every project is listed further down.

Project sizes

How many tiles each project took. A tile is the smallest piece of a Tiny Tapeout chip you can submit a design to.

Total	90
1 × 1 tiles	65
1 × 2 tiles	15
2 × 2 tiles	6
3 × 2 tiles	2
3 × 4 tiles	1
4 × 4 tiles	1

Layout on GitHub

Shuttle status

Two schedules meet here: Tiny Tapeout collects the projects and builds the die, then wafer.space manufactures it on wafer.space Run 2 and ships the parts.

Done so far

wafer.space 1 March 2026 Campaign opens Run 2 slots available for purchase on Crowd Supply
wafer.space 30 April 2026, 23:59 AoE Early bird deadline Last day to purchase at early bird pricing, for whole-die slots on the run (not Tiny Tapeout projects)
Tiny Tapeout 24 June 2026 Tiny Tapeout GF 26b submissions close Last day to submit a project to this Tiny Tapeout shuttle
wafer.space 30 June 2026, 23:59 AoE Purchase deadline Final deadline to purchase slots, for whole-die slots on the run (not Tiny Tapeout projects)
Tiny Tapeout 4 July 2026 Tiny Tapeout GF 26b tapeout release Tiny Tapeout publishes the die's layout (tapeout-ws2607) and sends it to wafer.space
wafer.space 14 July 2026, 23:59 AoE Submission deadline Final deadline to submit clean GDS
wafer.space 22 July 2026 Tape-out to GlobalFoundries GDS files delivered to GlobalFoundries for fabrication
wafer.space 30 July 2026 Masks released Masks approved and fabrication started
wafer.space 17 September 2026 First wafers returned An initial set of wafers back from GlobalFoundries
wafer.space 8 October 2026 First wafers diced The initial wafers cut into individual dies

Still to come

Today, 24 October 2026
wafer.space 22 October 2026 (expected) First dies sorted Dies from the initial wafers picked and sorted by project
wafer.space 22 October 2026 (expected) First bare dies shipped Initial bare dies shipped to customers
wafer.space 12 November 2026 (expected) First packaged parts shipped Initial chip-on-board packaged parts shipped
wafer.space 10 December 2026 (expected) Main wafer lot returned The first full lot of Run 2 wafers back from GlobalFoundries
wafer.space 31 December 2026 (expected) Main lot bare dies shipped Bare dies from the main lot shipped to customers
wafer.space 15 January 2027 (expected) Last wafer lot returned The rest of the Run 2 wafers back from GlobalFoundries
wafer.space 21 January 2027 (expected) Main lot packaged parts shipped Chip-on-board packaged parts from the main lot shipped
wafer.space 5 February 2027 (expected) Last lot bare dies shipped Bare dies from the last lot shipped to customers
wafer.space 26 February 2027 (expected) Last lot packaged parts shipped Chip-on-board packaged parts from the last lot shipped

Missed this one? Tiny Tapeout GF 26c and 26d take projects until 7 December 2026: submit a project.

From the wafer.space run schedule and the Tiny Tapeout GF 26b repository.

How people used their silicon

Where the area of 90 projects (9 mm² of silicon) actually went

45%

49%

Logic cells 45% — gates and flip-flops doing the design's actual work
SRAM <1% — memory macros
Filler and tap cells 49% — inserted by the tools to keep rows continuous and wells tied
Other 6% — routing channels, analog and custom layout, power grid and empty space

What people built

The kinds of design on this chip.

Other digital 47 Accelerators 11 Security 7 RISC-V and CPUs 6 Communications 6 Games 5 Analog and mixed-signal 3 First designs 1 Art and logos 1 FPGA 1 Test structures 1 Retro computing 1

Standard cell libraries

The ready-made gate libraries the designs were built from: how many tracks tall each cell is, and the voltage it runs at.

Standard cell library	Logic cells	Share
7t-5V gf180mcu_fd_sc_mcu7t5v0	147k	98%
AS 7t-3.3V gf180mcu_as_sc_mcu7t3v3	2k	2%

Area budget of every design

Each bar is one project, split the same way as above. Sorted by how much of the project is logic.

295 ASCON Integrated Crypto Processor 067 Car Trip 356 Arctic0 16-bit CPU 071 4-Neuron LIF Spiking Neural Network 195 LEA-128 551 BRISQ 354 PWM-Analyser 612 Detronyx Arithmetic Lab Tile 036 Neural Spike Detector 033 60 Hz Grid-Forming ASIC with Dump-Load Control 038 Lightscan 390 Smerity-Mandelbrot

Show all 90 projects

613 Simon Says memory game 288 100Mbps Ethernet Accelerator Wrapper 358 Pong 101 AER Reflex Chip - MCP2515 CAN gateway 610 PDM Voice Activity Detector 386 Elemental Harmony Game 549 Detronyx UART Trace Exerciser 517 I2C Slave Template with Emulated Sensor 100 Neuromorphic PUF (distinct-tap LFSR arbiter + memristor XOR, GF180) 103 Music for ASICs 581 Aswarby INT8 MAC 102 wafer.space Logo VGA Screensaver 135 2048 sliding tile puzzle game (VGA) 454 Spiking Neural Network WTA Inference Engine (GF180) 199 100Mbps 3 port Ethernet switch 453 Hardware UTF Encoder/Decoder 545 Quadrature sine generator 096 Asynchronous-AER Spike Router (4-phase REQ/ACK, 16-entry routing table, GF180) 450 Programmable Waveform and PWM Generator 098 CIM Controller with BIST and Fault Map (GF180) 547 Tiny RIng Oscillator PUF 034 Neuromorphic Spike Codec (GF180) 577 SPI-CPU 609 XORing given bits 039 ChaCha20 352 Procedural ASIC 005 spiPWMio 129 CWRU CHIPS Simple Counter with 7-segment Display 611 PolyTrig Digital Waveform Synthesis Core 512 SPI Slave with 8-Register File 614 Nearest Neighbor Interpolation 451 Universal Binary to Segment Decoder 485 Hardware Anomaly Detection 608 7SegmentDice 355 CORDIC sin/cos generator 069 triad01 359 Tremolo guitar pedal ASIC 519 BSD Convolution Adder Tree 578 ECC Scalar Accelerator 389 Traffic Light FSM 196 Fast Authentication Accelerator 032 8-bit Interactive ALU 518 PQC NTT Butterfly Core 357 Three Channel RGB PWM Controller 000 Chip ROM 194 ECC Processor 455 SPI Master Slave Communication 391 fibbonaci_tt 487 Multi-Protocol Communication Controller 514 4 bit Accumulator CPU 001 Tiny Tapeout Factory Test 385 PWM Generator 353 ttgf jct PoC 513 Project 387 WashingMachine_FSM 580 Configurable PWM Generator 516 Programmable Chaotic NLFSR 128 UART_SOC 449 Simple Sprinkler 486 V2X Collision Warning 007 ECC Scalar Multiplication 515 Simple SPI configuration for analog designs 483 AES S-Box Accelerator 480 Configurable 8-bit PWM Generator 481 Secure V2X Mini Demonstrator 579 I2C Master Controller 582 8-bit Comparator 198 TRNG using Ring Oscillator 484 8-bit LFSR Circuit 576 4-bit Maximum-Length LFSR 134 Secure TRNG Entropy Generator 192 ECDSA Verification 132 8-bit WNN Pattern Recognizer 130 Raksha 482 Digital Door Lock 003 TT-Arrakeen-SPSRAM-direct-sramrules 065 TT-Arrakeen-SPSRAM-direct-5V 583 TT-Arrakeen-SPSRAM-direct

Which parts of the process were used

Transistor voltages and optional devices across the 90 designs

Transistor voltages

3.3 V 4

5 V 88

A design counts for a voltage when its standard cells, SRAM or its own transistors use it. 5 V and 6 V transistors share the thick gate oxide; a marker layer in the layout tells them apart.

Optional devices drawn by designers

Not drawn by any design: Native transistors, 10 V LDMOS, MIM capacitors, MOS capacitors, High-resistance poly resistors, Unsalicided poly resistors, Salicided poly resistors, Diffusion resistors, N-well resistors, Metal resistors, Diodes, Well diodes, Deep N-well, Bipolar transistors, Schottky diodes, Zener diodes, eFuses, One-time programmable memory, Inductors.

Only devices outside standard cells, SRAM macros and I/O pads count, since every die has those. A single test structure counts the same as a large block.

Gate oxides

Transistors	Designs	Which
3.3 V and 5 V/6 V	2	TT-Arrakeen-SPSRAM-direct-sramrules, TT-Arrakeen-SPSRAM-direct
3.3 V only	2	Detronyx UART Trace Exerciser, Detronyx Arithmetic Lab Tile
5 V/6 V only	86	86 projects Chip ROM, Tiny Tapeout Factory Test, spiPWMio, ECC Scalar Multiplication, 8-bit Interactive ALU, 60 Hz Grid-Forming ASIC with Dump-Load Control, Neuromorphic Spike Codec (GF180), Neural Spike Detector, Lightscan, ChaCha20, TT-Arrakeen-SPSRAM-direct-5V, Car Trip, triad01, 4-Neuron LIF Spiking Neural Network, Asynchronous-AER Spike Router (4-phase REQ/ACK, 16-entry routing table, GF180), CIM Controller with BIST and Fault Map (GF180), Neuromorphic PUF (distinct-tap LFSR arbiter + memristor XOR, GF180), AER Reflex Chip - MCP2515 CAN gateway, wafer.space Logo VGA Screensaver, Music for ASICs, UART_SOC, CWRU CHIPS Simple Counter with 7-segment Display, Raksha, 8-bit WNN Pattern Recognizer, Secure TRNG Entropy Generator, 2048 sliding tile puzzle game (VGA), ECDSA Verification, ECC Processor, LEA-128, Fast Authentication Accelerator, TRNG using Ring Oscillator, 100Mbps 3 port Ethernet switch, 100Mbps Ethernet Accelerator Wrapper, ASCON Integrated Crypto Processor, Procedural ASIC, ttgf jct PoC, PWM-Analyser, CORDIC sin/cos generator, Arctic0 16-bit CPU, Three Channel RGB PWM Controller, Pong, Tremolo guitar pedal ASIC, PWM Generator, Elemental Harmony Game, WashingMachine_FSM, Traffic Light FSM, Smerity-Mandelbrot, fibbonaci_tt, Simple Sprinkler, Programmable Waveform and PWM Generator, Universal Binary to Segment Decoder, Hardware UTF Encoder/Decoder, Spiking Neural Network WTA Inference Engine (GF180), SPI Master Slave Communication, Configurable 8-bit PWM Generator, Secure V2X Mini Demonstrator, Digital Door Lock, AES S-Box Accelerator, 8-bit LFSR Circuit, Hardware Anomaly Detection, V2X Collision Warning, Multi-Protocol Communication Controller, SPI Slave with 8-Register File, Project, 4 bit Accumulator CPU, Simple SPI configuration for analog designs, Programmable Chaotic NLFSR, I2C Slave Template with Emulated Sensor, PQC NTT Butterfly Core, BSD Convolution Adder Tree, Quadrature sine generator, Tiny RIng Oscillator PUF, BRISQ, 4-bit Maximum-Length LFSR, SPI-CPU, ECC Scalar Accelerator, I2C Master Controller, Configurable PWM Generator, Aswarby INT8 MAC, 8-bit Comparator, 7SegmentDice, XORing given bits, PDM Voice Activity Detector, PolyTrig Digital Waveform Synthesis Core, Simon Says memory game, Nearest Neighbor Interpolation

3.3 V transistors have the thin gate oxide; 5 V and 6 V ones share the thick one.

What fits on 1 mm² of GF180MCU silicon?

Theoretical maximum against what designers achieved

The maximum packs one cell type edge to edge with no room for wiring. Real designs need the wiring. Each box gives the most of a cell that fits with any GF180MCU library, then with the libraries this chip used.

~114k

Inverters per mm²

GF180MCU maximum,
with AS 7t-3.3V inv_2

With this chip's libraries:

7t-5V: 114k inv_1

AS 7t-3.3V: 114k inv_2

~91k

NAND gates per mm²

GF180MCU maximum,
with 7t-5V nand2_1

With this chip's libraries:

7t-5V: 91k nand2_1

AS 7t-3.3V: 65k nand2_2

~76k

Buffers per mm²

GF180MCU maximum,
with AS 7t-3.3V buff_2

With this chip's libraries:

7t-5V: 76k buf_1

AS 7t-3.3V: 76k buff_2

~17k

Flip-flops per mm²

GF180MCU maximum,
with AS 7t-3.3V dfxtp_2

With this chip's libraries:

7t-5V: 16k dffq_1

AS 7t-3.3V: 17k dfxtp_2

34k

Best core average

logic cells/mm² of core — 45% of the buffer maximum

Car Trip

47k

Densest 0.1 mm square

logic cells per mm² — 61% of the buffer maximum

Tiny RIng Oscillator PUF

21k

Typical project

median logic cells/mm² of core across 36 digital projects (1,000 or more logic cells)

58% of the core covered by logic cells

Percentages compare with the buffer maximum for each design's own library: buffers are among the smallest and most common logic cells, so a design made only of buffers, packed edge to edge with no wiring, would reach 100%.

Sizing your own design

What each tile size held on this chip, and what it would hold at its densities

				Logic cells in its digital projects1,000 or more logic cells		Logic cells at this chip's density		Theoretical maximum, 7t-5V cells
Tiles	Size	Core area	Projects	Most	Median	Typical21k / mm²	Best34k / mm²	NAND gatesnand2_1	Flip-flopsdffq_1
1 × 1	0.35 × 0.16 mm	0.06 mm²	65	1.9k	1.3k	1.2k	1.9k	5.1k	880
1 × 2	0.35 × 0.33 mm	0.12 mm²	15	3.3k	2.4k	2.5k	3.9k	10.5k	1.8k
2 × 2	0.71 × 0.33 mm	0.23 mm²	6	6.8k	5.2k	5.0k	8.0k	21.3k	3.7k
3 × 2	1.08 × 0.33 mm	0.36 mm²	2	8.2k	7.5k	7.6k	12.1k	32.5k	5.6k
3 × 4	1.08 × 0.74 mm	0.80 mm²	1	11.7k	11.7k	17.0k	27.1k	72.8k	12.6k
4 × 4	1.44 × 0.74 mm	1.07 mm²	1	30.2k	30.2k	22.7k	36.2k	97.1k	16.7k

Swipe the table sideways for more columns.

Core area is the whole project. "Typical" and "best" multiply the core area by this chip's median and best core densities; SRAM and analog blocks take their area out of that. The theoretical maxima fill the core with nothing but that one cell of 7t-5V, the library most used on this chip, edge to edge with no routing.

Pick the tile size your design needs when you submit it to the next Tiny Tapeout chip, by 7 December 2026.

Logic density of every digital design

A digital project here is one with 1,000 or more logic cells. Solid bar: average over the core. Outlined bar: the densest 0.1 mm square outside SRAM, per mm² (a dash where memory covers most of the design). The scale ends at the buffer theoretical maximum (76k cells/mm²). The numbers are core / densest, in logic cells per mm².

067 Car Trip 34k / 40k 195 LEA-128 29k / 38k 036 Neural Spike Detector 29k / 41k 386 Elemental Harmony Game 28k / 44k 295 ASCON Integrated Crypto Processor 28k / 36k 551 BRISQ 28k / 33k 356 Arctic0 16-bit CPU 27k / 36k 071 4-Neuron LIF Spiking Neural Network 26k / 30k 354 PWM-Analyser 26k / 33k 390 Smerity-Mandelbrot 26k / 32k 612 Detronyx Arithmetic Lab Tile 25k / 32k 033 60 Hz Grid-Forming ASIC with Dump-Load Control 25k / 30k

Show all 36 digital projects

610 PDM Voice Activity Detector 24k / 29k 038 Lightscan 24k / 30k 613 Simon Says memory game 23k / 37k 358 Pong 23k / 29k 101 AER Reflex Chip - MCP2515 CAN gateway 23k / 28k 453 Hardware UTF Encoder/Decoder 22k / 36k 288 100Mbps Ethernet Accelerator Wrapper 21k / 26k 581 Aswarby INT8 MAC 20k / 29k 103 Music for ASICs 20k / 28k 102 wafer.space Logo VGA Screensaver 19k / 27k 135 2048 sliding tile puzzle game (VGA) 19k / 30k 517 I2C Slave Template with Emulated Sensor 19k / 23k 454 Spiking Neural Network WTA Inference Engine (GF180) 19k / 29k 547 Tiny RIng Oscillator PUF 19k / 47k 545 Quadrature sine generator 18k / 27k 100 Neuromorphic PUF (distinct-tap LFSR arbiter + memristor XOR, GF180) 17k / 26k 034 Neuromorphic Spike Codec (GF180) 16k / 28k 098 CIM Controller with BIST and Fault Map (GF180) 15k / 29k 450 Programmable Waveform and PWM Generator 15k / 29k 039 ChaCha20 15k / 35k 199 100Mbps 3 port Ethernet switch 14k / 31k 096 Asynchronous-AER Spike Router (4-phase REQ/ACK, 16-entry routing table, GF180) 14k / 23k 352 Procedural ASIC 14k / 30k 129 CWRU CHIPS Simple Counter with 7-segment Display 13k / 32k

Every digital project's densities as a table

Project	Tiles	Library	Logic cells	Inside core per mm²	Densest 0.1 mm square per mm²	Core covered	Core mm²
Car Trip 067	1 × 1	7t-5V	1,901	33,946	39,800	80%	0.06*
LEA-128 195	2 × 2	7t-5V	6,850	29,236	38,300	76%	0.23*
Neural Spike Detector 036	1 × 2	7t-5V	3,296	28,537	40,700	72%	0.12*
Elemental Harmony Game 386	2 × 2	7t-5V	6,656	28,408	43,800	60%	0.23*
ASCON Integrated Crypto Processor 295	4 × 4	7t-5V	30,184	28,326	36,000	83%	1.07*
BRISQ 551	1 × 1	7t-5V	1,555	27,768	32,600	76%	0.06*
Arctic0 16-bit CPU 356	1 × 2	7t-5V	3,152	27,290	35,800	79%	0.12*
4-Neuron LIF Spiking Neural Network 071	1 × 1	7t-5V	1,459	26,054	30,000	77%	0.06*
PWM-Analyser 354	1 × 2	7t-5V	2,960	25,628	32,700	76%	0.12*
Smerity-Mandelbrot 390	2 × 2	7t-5V	5,977	25,510	31,700	65%	0.23*
Detronyx Arithmetic Lab Tile 612	1 × 1	AS 7t-3.3V	1,427	25,482	32,400	74%	0.06*
60 Hz Grid-Forming ASIC with Dump-Load Control 033	1 × 2	7t-5V	2,936	25,420	30,300	70%	0.12*
PDM Voice Activity Detector 610	1 × 1	7t-5V	1,357	24,232	28,600	61%	0.06*
Lightscan 038	1 × 2	7t-5V	2,796	24,208	29,800	69%	0.12*
Simon Says memory game 613	1 × 1	7t-5V	1,301	23,232	37,200	64%	0.06*
Pong 358	1 × 2	7t-5V	2,680	23,203	28,700	63%	0.12*
AER Reflex Chip - MCP2515 CAN gateway 101	3 × 2	7t-5V	8,164	22,907	28,500	63%	0.36*
Hardware UTF Encoder/Decoder 453	1 × 1	7t-5V	1,220	21,786	36,100	51%	0.06*
100Mbps Ethernet Accelerator Wrapper 288	1 × 2	7t-5V	2,406	20,831	26,000	63%	0.12*
Aswarby INT8 MAC 581	1 × 1	7t-5V	1,146	20,464	28,700	53%	0.06*
Music for ASICs 103	1 × 2	7t-5V	2,360	20,433	27,800	53%	0.12*
wafer.space Logo VGA Screensaver 102	1 × 2	7t-5V	2,228	19,290	27,300	53%	0.12*
2048 sliding tile puzzle game (VGA) 135	3 × 2	7t-5V	6,736	18,900	30,000	53%	0.36*
I2C Slave Template with Emulated Sensor 517	1 × 1	7t-5V	1,051	18,768	23,100	56%	0.06*
Spiking Neural Network WTA Inference Engine (GF180) 454	2 × 2	7t-5V	4,367	18,638	28,700	53%	0.23*
Tiny RIng Oscillator PUF 547	1 × 1	7t-5V	1,039	18,554	46,600	46%	0.06*
Quadrature sine generator 545	1 × 1	7t-5V	1,017	18,161	27,400	50%	0.06*
Neuromorphic PUF (distinct-tap LFSR arbiter + memristor XOR, GF180) 100	1 × 2	7t-5V	1,971	17,065	26,500	55%	0.12*
Neuromorphic Spike Codec (GF180) 034	1 × 2	7t-5V	1,899	16,442	27,600	45%	0.12*
CIM Controller with BIST and Fault Map (GF180) 098	1 × 2	7t-5V	1,759	15,229	29,300	47%	0.12*
Programmable Waveform and PWM Generator 450	2 × 2	7t-5V	3,560	15,194	29,000	48%	0.23*
ChaCha20 039	3 × 4	7t-5V	11,717	14,661	35,300	38%	0.80*
100Mbps 3 port Ethernet switch 199	2 × 2	7t-5V	3,297	14,072	30,700	52%	0.23*
Asynchronous-AER Spike Router (4-phase REQ/ACK, 16-entry routing table, GF180) 096	1 × 2	7t-5V	1,594	13,801	23,000	49%	0.12*
Procedural ASIC 352	1 × 2	7t-5V	1,581	13,688	30,500	37%	0.12*
CWRU CHIPS Simple Counter with 7-segment Display 129	1 × 2	7t-5V	1,478	12,797	31,500	34%	0.12*

The projects

Every project on this chip: an index, then grouped by what it does. Select one for its layout, its measurements and any die photographs.

Project index

All 90 projects by their address on the chip's multiplexer, with how many tiles each took and how much logic it packs.

Address	Project	Author	Tiles	What it is	Logic cells	Cells per mm²
000	Chip ROM	Uri Shaked	1 × 1	Other digital	226	4k
001	Tiny Tapeout Factory Test	Tiny Tapeout	1 × 1	Test structures	108	2k
003	TT-Arrakeen-SPSRAM-direct-sramrules	Staf Verhaegen	1 × 1	Other digital	8	<1k
005	spiPWMio	Sönke Appel · repository @FHW-Appel	1 × 1	Other digital	710	13k
007	ECC Scalar Multiplication	Dhanush Kulkarni · repository @CambridgeinstitutetechnologyBLR-Dhanush	1 × 1	Other digital	65	1k
032	8-bit Interactive ALU	Matanel Kadosh · repository @matanelk96	1 × 1	RISC-V and CPUs	303	5k
033	60 Hz Grid-Forming ASIC with Dump-Load Control	Eric Pearson · repository @ericpearson1313	1 × 2	Accelerators	2,936	25k
034	Neuromorphic Spike Codec (GF180)	Prof. Santhosh Sivasubramani, IIT Delhi	1 × 2	Other digital	1,899	16k
036	Neural Spike Detector	Layla Adeli · repository @laylaadeli7	1 × 2	Accelerators	3,296	29k
038	Lightscan	Emilio Perez Juarez · repository @EmilioPeJu	1 × 2	Other digital	2,796	24k
039	ChaCha20	Raphael Eguchi · repository @egurapha	3 × 4	Security	11,717	15k
065	TT-Arrakeen-SPSRAM-direct-5V	Staf Verhaegen	1 × 1	Analog and mixed-signal	8	<1k
067	Car Trip	Luke Silva · repository @LukeSilva	1 × 1	Retro computing	1,901	34k
069	triad01	Duan Yihe · repository @Alanduan21	1 × 1	Other digital	402	7k
071	4-Neuron LIF Spiking Neural Network	Ilim Stankulov · repository @ilim-stankulov	1 × 1	Accelerators	1,459	26k
096	Asynchronous-AER Spike Router (4-phase REQ/ACK, 16-entry routing table, GF180)	Prof. Santhosh Sivasubramani, IIT Delhi	1 × 2	Other digital	1,594	14k
098	CIM Controller with BIST and Fault Map (GF180)	Prof. Santhosh Sivasubramani, IIT Delhi · repository @santhoshs93	1 × 2	Other digital	1,759	15k
100	Neuromorphic PUF (distinct-tap LFSR arbiter + memristor XOR, GF180)	Prof. Santhosh Sivasubramani, IIT Delhi · repository @santhoshs93	1 × 2	Security	1,971	17k
101	AER Reflex Chip - MCP2515 CAN gateway	khu-haeun · repository @khu-haeun	3 × 2	Communications	8,164	23k
102	wafer.space Logo VGA Screensaver	Uri Shaked	1 × 2	Art and logos	2,228	19k
103	Music for ASICs	d5smith · repository @d5smith	1 × 2	Other digital	2,360	20k
128	UART_SOC	Siri Jagadeesh · repository @sirijagadeesh4-hub	1 × 1	Communications	56	1k
129	CWRU CHIPS Simple Counter with 7-segment Display	Andrew Chen, John Paul Magbitang · repository @john-paul-sm	1 × 2	RISC-V and CPUs	1,478	13k
130	Raksha	Sinchana · repository @shanthkumars165-commits	1 × 1	Other digital	16	<1k
132	8-bit WNN Pattern Recognizer	Your Name · repository @cambridgeinstitutetechnology-blr-venkat	1 × 1	Accelerators	23	<1k
134	Secure TRNG Entropy Generator	Likitha · repository @Cambridgeinstituteoftechnology-likitha	1 × 1	Other digital	16	<1k
135	2048 sliding tile puzzle game (VGA)	Uri Shaked · repository @urish	3 × 2	Games	6,736	19k
192	ECDSA Verification	Lyra · repository @santoshism2006-pixel	1 × 1	Other digital	26	<1k
194	ECC Processor	Dhanush Kulkarni · repository @CambridgeinstitutetechnologyBLR-Dhanush	1 × 1	RISC-V and CPUs	183	3k
195	LEA-128	awayzer JCT · repository @awayzer	2 × 2	Security	6,850	29k
196	Fast Authentication Accelerator	Nagaraj · repository @CambridgeinstitutetechnolgyBLR-Harshini	1 × 1	Accelerators	252	5k
198	TRNG using Ring Oscillator	Karthik · repository @cambridgeinstituetechnologyBLR-karthikp	1 × 1	Other digital	27	<1k
199	100Mbps 3 port Ethernet switch	Julia Desmazes · repository @Essenceia	2 × 2	Communications	3,297	14k
288	100Mbps Ethernet Accelerator Wrapper	Julia Desmazes · repository @Essenceia	1 × 2	Accelerators	2,406	21k
295	ASCON Integrated Crypto Processor	Dr. Mohamed El-Hadedy · repository @mealycpp	4 × 4	Security	30,184	28k
352	Procedural ASIC	Conner Daehler	1 × 2	Other digital	1,581	14k
353	ttgf jct PoC	awayzer JCT · repository @awayzer	1 × 1	Security	101	2k
354	PWM-Analyser	Pauline Kreis, Muhammad Saim Bilal · repository @PaulineKreis	1 × 2	Other digital	2,960	26k
355	CORDIC sin/cos generator	Jacques Te · repository @JacquesBTe	1 × 1	Accelerators	434	8k
356	Arctic0 16-bit CPU	Einosuke Okazaki · repository @PenguinEino	1 × 2	RISC-V and CPUs	3,152	27k
357	Three Channel RGB PWM Controller	Aiden Koch · repository @aidenkoch4	1 × 1	Other digital	191	3k
358	Pong	Lukas Hahne · repository @ljhahne	1 × 2	Games	2,680	23k
359	Tremolo guitar pedal ASIC	Preston Schuetz · repository @Pschuetz112	1 × 1	Other digital	356	6k
385	PWM Generator	Omar, Nitin · repository @Omar90551	1 × 1	Other digital	118	2k
386	Elemental Harmony Game	Aakarshitha Suresh · repository @Aakarshitha	2 × 2	Games	6,656	28k
387	WashingMachine_FSM	Charithma Perera, Kim Luu · repository @KimLuu02	1 × 1	Other digital	108	2k
389	Traffic Light FSM	Eric Kiecksee · repository @Kieckenwama	1 × 1	Other digital	296	5k
390	Smerity-Mandelbrot	Stephen Merity · repository @Smerity	2 × 2	FPGA	5,977	26k
391	fibbonaci_tt	Jake Sabree	1 × 1	Other digital	150	3k
449	Simple Sprinkler	Noah Perez · repository @noahzperez29	1 × 1	Other digital	159	3k
450	Programmable Waveform and PWM Generator	silicon_nomad · repository @silicon-nomad	2 × 2	Analog and mixed-signal	3,560	15k
451	Universal Binary to Segment Decoder	Rebecca G. Bettencourt · repository @RebeccaRGB	1 × 1	Other digital	606	11k
453	Hardware UTF Encoder/Decoder	Rebecca G. Bettencourt · repository @RebeccaRGB	1 × 1	Other digital	1,220	22k
454	Spiking Neural Network WTA Inference Engine (GF180)	Prof. Santhosh Sivasubramani, IIT Delhi	2 × 2	Accelerators	4,367	19k
455	SPI Master Slave Communication	Nevin Philip · repository @nev-1910	1 × 1	Communications	128	2k
480	Configurable 8-bit PWM Generator	Vinuta	1 × 1	Other digital	57	1k
481	Secure V2X Mini Demonstrator	Pushkar Kulkarni · repository @push-777	1 × 1	Other digital	31	1k
482	Digital Door Lock	Rameshwar · repository @Rameshwar-12	1 × 1	Other digital	9	<1k
483	AES S-Box Accelerator	Santosh · repository @cambridgeinstitutetechnologyblr-santosh	1 × 1	Accelerators	62	1k
484	8-bit LFSR Circuit	Satya Roop Bankuru · repository @CambridgeinstitutetechnologyBLR-satya	1 × 1	Other digital	16	<1k
485	Hardware Anomaly Detection	Vinayak · repository @vinayakalk25	1 × 1	Accelerators	450	8k
486	V2X Collision Warning	PM Likhith Kumar	1 × 1	Other digital	115	2k
487	Multi-Protocol Communication Controller	Chirantan J Tilavalli · repository @CambridgeinstituteoftechnologyBLR-chiru	1 × 1	Communications	110	2k
512	SPI Slave with 8-Register File	Usha · repository @Ushaop-op	1 × 1	Other digital	467	8k
513	Project	DHR · repository @DRosen766	1 × 1	Other digital	115	2k
514	4 bit Accumulator CPU	Darshan	1 × 1	RISC-V and CPUs	101	2k
515	Simple SPI configuration for analog designs	Alan G · repository @agurlask	1 × 1	Analog and mixed-signal	56	1k
516	Programmable Chaotic NLFSR	Aishu · repository @CambridgeinstitutetechnologyBLR-Aishu	1 × 1	Security	82	1k
517	I2C Slave Template with Emulated Sensor	Sebastian Budde, Janina Speckmann · repository @BastiBudde	1 × 1	First designs	1,051	19k
518	PQC NTT Butterfly Core	Aishwarya Gadela & Bojji Reddy Rishika · repository @bojjireddyrishika12-web	1 × 1	Other digital	279	5k
519	BSD Convolution Adder Tree	Vincent Mertens · repository @Vincent2405	1 × 1	Other digital	355	6k
545	Quadrature sine generator	Framcesco Osti · repository @fran-retfie	1 × 1	Other digital	1,017	18k
547	Tiny RIng Oscillator PUF	Manuel Roales · repository @mRoales	1 × 1	Security	1,039	19k
549	Detronyx UART Trace Exerciser	Detronyx contributors · repository @Zhekar1998	1 × 1	Communications	978	17k
551	BRISQ	Poiku · repository @pratyaygopal	1 × 1	Other digital	1,555	28k
576	4-bit Maximum-Length LFSR	Geeta Doddamani · repository @Geeta-doddamani	1 × 1	Other digital	21	<1k
577	SPI-CPU	MS College of Engineering · repository @cyrilprasannarajp	1 × 1	RISC-V and CPUs	843	15k
578	ECC Scalar Accelerator	PM LIKHITH KUMAR AND PRAJWAL T · repository @pmlikhithkumar55-ship-it	1 × 1	Accelerators	325	6k
579	I2C Master Controller	Akshaya Institute of Technology · repository @abhilash0419	1 × 1	Other digital	46	1k
580	Configurable PWM Generator	Shivaranjani GR, Ganesh Ragava, Sidharth Kamalakkannan · repository @ShivaranjaniGR	1 × 1	Other digital	82	1k
581	Aswarby INT8 MAC	Mark Shilton · repository @markd666	1 × 1	Other digital	1,146	20k
582	8-bit Comparator	Nagaraj	1 × 1	Other digital	57	1k
583	TT-Arrakeen-SPSRAM-direct	Staf Verhaegen	1 × 1	Other digital	8	<1k
608	7SegmentDice	Jannis Rohleder, Aishwarya Kanade · repository @elvtide01	1 × 1	Games	538	10k
609	XORing given bits	Jan Cerny · repository @cherny1001	1 × 1	Other digital	837	15k
610	PDM Voice Activity Detector	Kevin · repository @antimatter15	1 × 1	Other digital	1,357	24k
611	PolyTrig Digital Waveform Synthesis Core	Saeed Seyedfaraji · repository @SaeedSeyedfaraji	1 × 1	Other digital	601	11k
612	Detronyx Arithmetic Lab Tile	Detronyx contributors · repository @Zhekar1998	1 × 1	Other digital	1,427	25k
613	Simon Says memory game	Uri Shaked · repository @urish	1 × 1	Games	1,301	23k
614	Nearest Neighbor Interpolation	Dan Mangum · repository @hasheddan	1 × 1	Other digital	583	10k

Show all 90 projectsShow the first 16 only

Swipe the table sideways for more columns.

Designs that grew

Some designs on this chip have been made many times, on earlier and later Tiny Tapeout chips, and several now have a whole die of their own on a wafer.space run. The ringed marker is this chip.

Expresso Ethernet switch 199, 288

Tiny Tapeout tile Google shuttle wafer.space die this chip
Each marker is one version of the design: hover over it or focus it for details, and select it to open its page. On a phone, the table below lists every one.

As a table

Design	Made on	When	Version	Size
Expresso Ethernet switch	Tiny Tapeout GF 0.3	Jun 2026	Until heat death do us part	2 × 2 tiles
	Tiny Tapeout GF 26b	Jun 2026	100Mbps 3 port Ethernet switch; 100Mbps Ethernet Accelerator Wrapper	2 × 2 tiles, 1 × 2 tiles
	wafer.space Run 2	Jul 2026	CAFE Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version	½ × ½ slot

Other digital 47

Chip ROM

1 × 1 tile · 226 logic cells

5 V

TT-Arrakeen-SPSRAM-direct-sramrules

1 × 1 tile · 8 logic cells · custom SRAM

3.3 V · 5 V

spiPWMio

1 × 1 tile · 710 logic cells

5 V

ECC Scalar Multiplication

1 × 1 tile · 65 logic cells

5 V

Neuromorphic Spike Codec (GF180)

1 × 2 tiles · 2k logic cells

5 V

Lightscan

1 × 2 tiles · 3k logic cells

5 V

triad01

1 × 1 tile · 402 logic cells

5 V

Asynchronous-AER Spike Router (4-phase REQ/ACK, 16-entry routing table, GF180)

1 × 2 tiles · 2k logic cells

5 V

CIM Controller with BIST and Fault Map (GF180)

1 × 2 tiles · 2k logic cells

5 V

Music for ASICs

1 × 2 tiles · 2k logic cells

5 V

Raksha

1 × 1 tile · 16 logic cells

5 V

Secure TRNG Entropy Generator

1 × 1 tile · 16 logic cells

5 V

Show all 47 in Other digital

ECDSA Verification

1 × 1 tile · 26 logic cells

5 V

TRNG using Ring Oscillator

1 × 1 tile · 27 logic cells

5 V

Procedural ASIC

1 × 2 tiles · 2k logic cells

5 V

PWM-Analyser

1 × 2 tiles · 3k logic cells

5 V

Three Channel RGB PWM Controller

1 × 1 tile · 191 logic cells

5 V

Tremolo guitar pedal ASIC

1 × 1 tile · 356 logic cells

5 V

PWM Generator

1 × 1 tile · 118 logic cells

5 V

WashingMachine_FSM

1 × 1 tile · 108 logic cells

5 V

Traffic Light FSM

1 × 1 tile · 296 logic cells

5 V

fibbonaci_tt

1 × 1 tile · 150 logic cells

5 V

Simple Sprinkler

1 × 1 tile · 159 logic cells

5 V

Universal Binary to Segment Decoder

1 × 1 tile · 606 logic cells

5 V

Hardware UTF Encoder/Decoder

1 × 1 tile · 1k logic cells

5 V

Configurable 8-bit PWM Generator

1 × 1 tile · 57 logic cells

5 V

Secure V2X Mini Demonstrator

1 × 1 tile · 31 logic cells

5 V

Digital Door Lock

1 × 1 tile · 9 logic cells

5 V

8-bit LFSR Circuit

1 × 1 tile · 16 logic cells

5 V

V2X Collision Warning

1 × 1 tile · 115 logic cells

5 V

SPI Slave with 8-Register File

1 × 1 tile · 467 logic cells

5 V

Project

1 × 1 tile · 115 logic cells

5 V

PQC NTT Butterfly Core

1 × 1 tile · 279 logic cells

5 V

BSD Convolution Adder Tree

1 × 1 tile · 355 logic cells

5 V

Quadrature sine generator

1 × 1 tile · 1k logic cells

5 V

BRISQ

1 × 1 tile · 2k logic cells

5 V

4-bit Maximum-Length LFSR

1 × 1 tile · 21 logic cells

5 V

I2C Master Controller

1 × 1 tile · 46 logic cells

5 V

Configurable PWM Generator

1 × 1 tile · 82 logic cells

5 V

Aswarby INT8 MAC

1 × 1 tile · 1k logic cells

5 V

8-bit Comparator

1 × 1 tile · 57 logic cells

5 V

TT-Arrakeen-SPSRAM-direct

1 × 1 tile · 8 logic cells

3.3 V · 5 V

XORing given bits

1 × 1 tile · 837 logic cells

5 V

PDM Voice Activity Detector

1 × 1 tile · 1k logic cells

5 V

PolyTrig Digital Waveform Synthesis Core

1 × 1 tile · 601 logic cells

5 V

Detronyx Arithmetic Lab Tile

1 × 1 tile · 1k logic cells

3.3 V

Nearest Neighbor Interpolation

1 × 1 tile · 583 logic cells

5 V

Accelerators 11

60 Hz Grid-Forming ASIC with Dump-Load Control

1 × 2 tiles · 3k logic cells

5 V

Neural Spike Detector

1 × 2 tiles · 3k logic cells

5 V

4-Neuron LIF Spiking Neural Network

1 × 1 tile · 1k logic cells

5 V

8-bit WNN Pattern Recognizer

1 × 1 tile · 23 logic cells

5 V

Fast Authentication Accelerator

1 × 1 tile · 252 logic cells

5 V

100Mbps Ethernet Accelerator Wrapper

1 × 2 tiles · 2k logic cells

5 V

CORDIC sin/cos generator

1 × 1 tile · 434 logic cells

5 V

Spiking Neural Network WTA Inference Engine (GF180)

2 × 2 tiles · 4k logic cells

5 V

AES S-Box Accelerator

1 × 1 tile · 62 logic cells

5 V

Hardware Anomaly Detection

1 × 1 tile · 450 logic cells

5 V

ECC Scalar Accelerator

1 × 1 tile · 325 logic cells

5 V

Security 7

ChaCha20

3 × 4 tiles · 12k logic cells

5 V

Neuromorphic PUF (distinct-tap LFSR arbiter + memristor XOR, GF180)

1 × 2 tiles · 2k logic cells

5 V

LEA-128

2 × 2 tiles · 7k logic cells

5 V

ASCON Integrated Crypto Processor

4 × 4 tiles · 30k logic cells

5 V

ttgf jct PoC

1 × 1 tile · 101 logic cells

5 V

Programmable Chaotic NLFSR

1 × 1 tile · 82 logic cells

5 V

Tiny RIng Oscillator PUF

1 × 1 tile · 1k logic cells

5 V

RISC-V and CPUs 6

8-bit Interactive ALU

1 × 1 tile · 303 logic cells

5 V

CWRU CHIPS Simple Counter with 7-segment Display

1 × 2 tiles · 1k logic cells

5 V

ECC Processor

1 × 1 tile · 183 logic cells

5 V

Arctic0 16-bit CPU

1 × 2 tiles · 3k logic cells

5 V

4 bit Accumulator CPU

1 × 1 tile · 101 logic cells

5 V

SPI-CPU

1 × 1 tile · 843 logic cells

5 V

Communications 6

AER Reflex Chip - MCP2515 CAN gateway

3 × 2 tiles · 8k logic cells

5 V

UART_SOC

1 × 1 tile · 56 logic cells

5 V

100Mbps 3 port Ethernet switch

2 × 2 tiles · 3k logic cells

5 V

SPI Master Slave Communication

1 × 1 tile · 128 logic cells

5 V

Multi-Protocol Communication Controller

1 × 1 tile · 110 logic cells

5 V

Detronyx UART Trace Exerciser

1 × 1 tile · 978 logic cells

3.3 V

Games 5

2048 sliding tile puzzle game (VGA)

3 × 2 tiles · 7k logic cells

5 V

Pong

1 × 2 tiles · 3k logic cells

5 V

Elemental Harmony Game

2 × 2 tiles · 7k logic cells

5 V

7SegmentDice

1 × 1 tile · 538 logic cells

5 V

Simon Says memory game

1 × 1 tile · 1k logic cells

5 V

Analog and mixed-signal 3

TT-Arrakeen-SPSRAM-direct-5V

1 × 1 tile · 8 logic cells

5 V

Programmable Waveform and PWM Generator

2 × 2 tiles · 4k logic cells

5 V

Simple SPI configuration for analog designs

1 × 1 tile · 56 logic cells

5 V

First designs 1

I2C Slave Template with Emulated Sensor

1 × 1 tile · 1k logic cells

5 V

Art and logos 1

102

wafer.space Logo VGA Screensaver

1 × 2 tiles · 2k logic cells

5 V

FPGA 1

Smerity-Mandelbrot

2 × 2 tiles · 6k logic cells

5 V

Test structures 1

Tiny Tapeout Factory Test

1 × 1 tile · 108 logic cells

5 V

Retro computing 1

Car Trip

1 × 1 tile · 2k logic cells

5 V

Die T26B on wafer.space Run 2

The die as a whole, measured like every other design on its run: its size, pads, process features, density, precheck and photographs. See every design on wafer.space Run 2

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core logic cells per mm²	12k (16% of buffer maximum) over the 12.90 mm² core: what the design itself packed
Inside the seal ring logic cells per mm²	8k over all 19.65 mm² of the slot, pad ring included
Densest mm² logic cells per mm²	25k (32% of buffer maximum)
Core covered by logic	35%
Transistor density transistors per mm²	227k average, 306k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Source repository

Die	3.93 × 5.12 mm (20.1 mm²)
Core area	12.90 mm² inside the pad ring the project template's, 442 µm in from each edge
Inside the seal ring	19.65 mm² (the die less its 26 µm seal ring)
Placements	1 on the reticle, in slot B3
Bond pads	74
Transistors	2,927,843
Logic cells	155,961 + 329,068 filler and tap cells
Libraries	7t-5V (154k), AS 7t-3.3V (2k)
SRAM	custom layout

Submission

Licence	Apache-2.0 declared Repository: Apache-2.0 in LICENSE — agrees
How it was checked	Commit and PDK pin The licence and template were read from the repository at commit 8c92b24e237f.
Chip-on-board	Not selected at submission
Precheck	Passed the check it was accepted on, 2026-07-04 Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 V	AS 7t-3.3V standard cells, 38,977 custom transistors
5 V	7t-5V standard cells, 7,382 custom transistors
Gate oxides	Thin (3.3 V) and thick (5 V/6 V) in the design itself
I/O library	gf180mcu_ocd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and pad ring.

22%

29%

13%

36%

Logic cells 4.47 mm² (22%)
Filler and tap cells 5.87 mm² (29%)
Other 2.56 mm² (13%)
Pad ring 7.22 mm² (36%)

Most used cells

The ten standard cells this design uses most.

Cell	Library	Instances	What it does
nand2_1	7t-5V	16,096	2-input NAND gate
oai21_1	7t-5V	9,720	OR-AND-Invert compound gate
dffq_1	7t-5V	9,396	D flip-flop (1 bit storage)
nor2_1	7t-5V	9,393	2-input NOR gate
clkinv_1	7t-5V	9,188	Clock inverter
dffrnq_1	7t-5V	7,995	D flip-flop with reset
dlyb_1	7t-5V	7,963	Delay buffer
aoi21_1	7t-5V	7,798	AND-OR-Invert compound gate
buf_2	7t-5V	5,436	Buffer (2x drive)
aoi22_1	7t-5V	5,356	AND-OR-Invert (2x2 inputs)

Logic density map

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (25k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. T26B was accepted on this check, and has been checked again since with newer rules.

All 16 steps passed, with 0 KLayout DRC errors, on 2026-07-04.

Every step, and the latest re-run

Step	Accepted on check 335, 2026-07-04, initial	Latest re-run check 740, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayout	passed	passed
KLayout.CheckTopLevel	passed	passed
KLayout.CheckSize	passed	passed
KLayout.GenerateID	passed	passed
KLayout.Render	passed	passed
KLayout.Density	passed	passed
Checker.KLayoutDensity	passed	passed
KLayout.ZeroAreaPolygons	passed	passed
Checker.KLayoutZeroAreaPolygons	passed	passed
KLayout.Antenna	passed	passed
Checker.KLayoutAntenna	passed	passed
Magic.DRC	passed	passed
Checker.MagicDRC	advisory warning	advisory warning
KLayout.DRC	passed	passed
Checker.KLayoutDRC	passed	passed
KLayout.WriteLayout	passed	passed
KLayout DRC errors	0	0
Magic DRC errors (advisory)	42,336	42,336
Files	steps · log (gzip)	steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Data and method

Everything on this page is measured from the public layout; the dates come from the published schedules.

Logic cells are standard cell instances, excluding fillers, taps, antenna diodes and tie cells.
Transistors are places where gate polysilicon crosses diffusion, not counting dummy fill.
Core area is the whole project.
Bond pads are the pad openings in the pad ring, or in a second ring of pads inside it for chip-on-board bonding; probe pads are the others, next to the blocks they test. Letters and logos on the pad layer are not pads.
Theoretical maximum tiles one cell at its placement boundary with no routing.
Densest 0.1 mm square is the best 0.1 mm square anywhere in each die, sliding in 20 µm steps and avoiding SRAM, given per mm².

The full written analysis is the density report. The measurements behind it:

Generated by ws-run-reports from layout/T26B.oas (md5 a905e364075a3362a8629aee939dd5e6).

What is Tiny Tapeout?

Tiny Tapeout is the quickest and cheapest way to get your own design made on a real chip.

Many designs share one Tiny Tapeout chip. Each project gets one or more small tiles, and a multiplexer on the chip connects the one you choose to the pins. Draw your first design in the browser with no experience by following the digital design guide, or write it in Verilog or another HDL; Tiny Tapeout's templates build and check it on GitHub. The chip comes on a demo board that selects your design and drives it.

Tiny Tapeout also runs workshops and supports teaching in universities and schools. Browse every Tiny Tapeout chip and the projects proven in silicon, or read the Tiny Tapeout FAQ.

Buy a chip and board All its projects on tinytapeout.com

The Tiny Tapeout demo board, with the socket in the middle where the chip's breakout card plugs in — Tiny Tapeout chips come on a breakout card that plugs into the middle of the demo board. Its RP2350 selects a project and drives its clock; the DIP switches, the seven-segment display and the Pmod headers connect to the project's pins. Render: Tiny Tapeout, tt-demo-pcb, Apache 2.0.

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.