Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

ChaCha20

039 · Security · 3 × 4 tiles

by Raphael Eguchi

Layout render of ChaCha20

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		15k (19% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		35k (46% of buffer maximum)
Core covered by logic38%
Transistor density
transistors per mm²		262k average, 322k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

RFC 8439 ChaCha20 stream-cipher core with a UART or parallel host interface

Source repository Its page on Tiny TapeoutBuy a chip and board

Size1076 × 737 µm (0.793 mm²)
Macrott_um_egurapha_chacha20
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles3 × 4 at column 0, row 11 of the tile grid
Mux address39
LanguageSystemVerilog
Clock35 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors209,343
Logic cells11,717 + 25,725 filler and tap cells
Libraries 7t-5V (12k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

38%
60%
  • Logic cells 0.30 mm² (38%)
  • Filler and tap cells 0.48 mm² (60%)
  • Other 0.02 mm² (2%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1,4692-input NAND gate
dffq_17t-5V 1,037D flip-flop (1 bit storage)
aoi22_17t-5V 767AND-OR-Invert (2x2 inputs)
aoi21_17t-5V 682AND-OR-Invert compound gate
clkinv_17t-5V 673Clock inverter
mux2_27t-5V 6302-input multiplexer (2x drive)
buf_27t-5V 562Buffer (2x drive)
oai21_17t-5V 556OR-AND-Invert compound gate
clkbuf_27t-5V 539Clock buffer (2x drive)
dlyb_17t-5V 491Delay buffer

Logic density map

0 logic cells, 2,031 transistors 0 logic cells, 2,128 transistors 0 logic cells, 2,105 transistors 0 logic cells, 2,131 transistors 0 logic cells, 2,103 transistors 0 logic cells, 2,128 transistors 0 logic cells, 2,129 transistors 0 logic cells, 2,130 transistors 0 logic cells, 2,127 transistors 0 logic cells, 2,128 transistors 0 logic cells, 1,470 transistors 0 logic cells, 2,117 transistors 11 logic cells, 2,260 transistors 61 logic cells, 2,514 transistors 102 logic cells, 2,531 transistors 97 logic cells, 2,470 transistors 127 logic cells, 2,678 transistors 115 logic cells, 2,652 transistors 67 logic cells, 2,358 transistors 0 logic cells, 2,219 transistors 0 logic cells, 2,218 transistors 1 logic cells, 1,532 transistors 4 logic cells, 2,124 transistors 167 logic cells, 2,755 transistors 271 logic cells, 3,015 transistors 299 logic cells, 3,150 transistors 286 logic cells, 3,236 transistors 277 logic cells, 3,041 transistors 271 logic cells, 3,081 transistors 218 logic cells, 3,096 transistors 178 logic cells, 2,843 transistors 99 logic cells, 2,684 transistors 6 logic cells, 1,584 transistors 81 logic cells, 2,584 transistors 267 logic cells, 2,922 transistors 346 logic cells, 3,130 transistors 259 logic cells, 3,064 transistors 107 logic cells, 2,462 transistors 149 logic cells, 2,724 transistors 144 logic cells, 2,602 transistors 210 logic cells, 2,880 transistors 303 logic cells, 3,094 transistors 284 logic cells, 3,071 transistors 103 logic cells, 1,945 transistors 67 logic cells, 2,458 transistors 260 logic cells, 3,010 transistors 342 logic cells, 3,144 transistors 295 logic cells, 3,271 transistors 228 logic cells, 2,792 transistors 147 logic cells, 2,691 transistors 162 logic cells, 2,715 transistors 190 logic cells, 2,741 transistors 292 logic cells, 3,227 transistors 303 logic cells, 3,236 transistors 157 logic cells, 2,137 transistors 100 logic cells, 2,393 transistors 253 logic cells, 2,818 transistors 281 logic cells, 3,161 transistors 308 logic cells, 3,235 transistors 312 logic cells, 3,117 transistors 234 logic cells, 2,903 transistors 220 logic cells, 2,836 transistors 330 logic cells, 3,082 transistors 303 logic cells, 3,216 transistors 189 logic cells, 2,756 transistors 28 logic cells, 1,641 transistors 157 logic cells, 2,551 transistors 236 logic cells, 2,884 transistors 218 logic cells, 2,976 transistors 206 logic cells, 2,893 transistors 172 logic cells, 2,887 transistors 198 logic cells, 2,928 transistors 173 logic cells, 2,749 transistors 145 logic cells, 2,700 transistors 80 logic cells, 2,705 transistors 4 logic cells, 2,245 transistors 0 logic cells, 1,528 transistors 13 logic cells, 724 transistors 75 logic cells, 975 transistors 97 logic cells, 1,014 transistors 32 logic cells, 838 transistors 0 logic cells, 727 transistors 0 logic cells, 737 transistors 0 logic cells, 736 transistors 0 logic cells, 739 transistors 0 logic cells, 734 transistors 0 logic cells, 737 transistors 0 logic cells, 510 transistors Densest SRAM-free 0.1 mm square: 353 logic cells 0 0 0 0 0 0 0 0 0 0 0 0 1k 6k 10k 10k 13k 11k 7k 0 0 <1k <1k 17k 27k 30k 29k 28k 27k 22k 18k 10k 1k 8k 27k 35k 26k 11k 15k 14k 21k 30k 28k 10k 7k 26k 34k 29k 23k 15k 16k 19k 29k 30k 16k 10k 25k 28k 31k 31k 23k 22k 33k 30k 19k 3k 16k 24k 22k 21k 17k 20k 17k 14k 8k <1k 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (35k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

← 038 Lightscan All projects TT-Arrakeen-SPSRAM-direct-5V 065 →