Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

Lightscan

038 · Other digital · 1 × 2 tiles

by Emilio Perez Juarez

Layout render of Lightscan

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		24k (32% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		30k (39% of buffer maximum)
Core covered by logic69%
Transistor density
transistors per mm²		289k average, 316k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

BISS-C Position acquisition system for a scan with pulsed output.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_emiliopeju_lightscan
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles1 × 2 at column 0, row 10 of the tile grid
Mux address38
LanguageVerilog
Clock12 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors33,377
Logic cells2,796 + 3,939 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

69%
25%
  • Logic cells 0.08 mm² (69%)
  • Filler and tap cells 0.03 mm² (25%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 490D flip-flop (1 bit storage)
oai21_17t-5V 269OR-AND-Invert compound gate
aoi21_17t-5V 204AND-OR-Invert compound gate
nor2_17t-5V 2042-input NOR gate
clkinv_17t-5V 183Clock inverter
nand2_17t-5V 1562-input NAND gate
dlyb_17t-5V 140Delay buffer
aoi22_17t-5V 132AND-OR-Invert (2x2 inputs)
buf_17t-5V 84Buffer
clkbuf_27t-5V 84Clock buffer (2x drive)

Logic density map

252 logic cells, 2,793 transistors 240 logic cells, 2,918 transistors 238 logic cells, 2,967 transistors 108 logic cells, 1,358 transistors 263 logic cells, 2,974 transistors 256 logic cells, 3,053 transistors 238 logic cells, 3,176 transistors 114 logic cells, 1,326 transistors 250 logic cells, 3,031 transistors 266 logic cells, 3,147 transistors 253 logic cells, 3,102 transistors 114 logic cells, 1,266 transistors 63 logic cells, 640 transistors 58 logic cells, 661 transistors 59 logic cells, 693 transistors 24 logic cells, 272 transistors Densest SRAM-free 0.1 mm square: 298 logic cells 25k 24k 24k 26k 26k 24k 25k 27k 25k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (30k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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