Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

CWRU CHIPS Simple Counter with 7-segment Display

129 · RISC-V and CPUs · 1 × 2 tiles

by Andrew Chen, John Paul Magbitang

Layout render of CWRU CHIPS Simple Counter with 7-segment Display

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		13k (17% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		32k (41% of buffer maximum)
Core covered by logic34%
Transistor density
transistors per mm²		247k average, 326k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Simple counter demo on a RISC-V CPU with 7-segment display output

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_cwru_cpu
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles1 × 2 at column 3, row 6 of the tile grid
Mux address129
LanguageVerilog
Clock5 Hz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors28,568
Logic cells1,478 + 3,388 filler and tap cells
Libraries 7t-5V (1k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

34%
59%
  • Logic cells 0.04 mm² (34%)
  • Filler and tap cells 0.07 mm² (59%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nor2_17t-5V 2062-input NOR gate
oai21_17t-5V 189OR-AND-Invert compound gate
nand2_17t-5V 1802-input NAND gate
dffq_17t-5V 142D flip-flop (1 bit storage)
aoi21_17t-5V 119AND-OR-Invert compound gate
dlyb_17t-5V 80Delay buffer
clkinv_17t-5V 51Clock inverter
buf_27t-5V 44Buffer (2x drive)
or2_17t-5V 402-input OR gate
clkbuf_27t-5V 35Clock buffer (2x drive)

Logic density map

2 logic cells, 2,032 transistors 72 logic cells, 2,299 transistors 71 logic cells, 2,267 transistors 11 logic cells, 914 transistors 64 logic cells, 2,319 transistors 275 logic cells, 3,096 transistors 290 logic cells, 3,255 transistors 78 logic cells, 1,246 transistors 75 logic cells, 2,373 transistors 225 logic cells, 2,971 transistors 243 logic cells, 3,032 transistors 46 logic cells, 1,097 transistors 0 logic cells, 446 transistors 25 logic cells, 548 transistors 0 logic cells, 471 transistors 1 logic cells, 202 transistors Densest SRAM-free 0.1 mm square: 315 logic cells <1k 7k 7k 6k 27k 29k 7k 22k 24k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (32k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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