Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2
Raksha
130 · Other digital · 1 × 1 tile
by Sinchana · repository @shanthkumars165-commits
Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
16 logic cells: too few for density figures, which are given for projects of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
Secure Packet Authentication Engine for V2X Communication
Source repository Its page on Tiny TapeoutBuy a chip and board
| Size | 347 × 161 µm (0.056 mm²) |
|---|---|
| Macro | tt_um_raksha |
| Files | documentation · licence · layout and netlist in Tiny Tapeout GF 26b |
| Tiles | 1 × 1 at column 2, row 7 of the tile grid |
| Mux address | 130 |
| Language | Verilog |
| Clock | 1 MHz |
| Built with | LibreLane 3.0.3, open_pdks 54435919abff |
| Transistors | 11,392 |
| Logic cells | 16 + 1,272 filler and tap cells |
| Libraries | 7t-5V (16) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.