Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

Spiking Neural Network WTA Inference Engine (GF180)

454 · Accelerators · 2 × 2 tiles

by Prof. Santhosh Sivasubramani, IIT Delhi

Layout render of Spiking Neural Network WTA Inference Engine (GF180)

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		19k (25% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		29k (38% of buffer maximum)
Core covered by logic53%
Transistor density
transistors per mm²		279k average, 299k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

GF180mcuD digital spiking neural network inference engine: 4 LIF neurons with programmable 4x4 signed synaptic weight matrix, per-neuron bias, programmable global threshold/leak/refractory, hard winner-take-all lateral inhibition, optional self-recurrence, SPI-configurable 16-bit register file, 4-channel 2-bit input current coding, 4 spike outputs, 2-bit winner ID output, any-spike and busy flags; deterministic single-cycle neuron update

Source repository no longer public Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_santhosh_snn_wta_gf
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles2 × 2 at column 7, row 3 of the tile grid
Mux address454
LanguageVerilog
Clock25 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors65,373
Logic cells4,367 + 7,925 filler and tap cells
Libraries 7t-5V (4k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

53%
42%
  • Logic cells 0.12 mm² (53%)
  • Filler and tap cells 0.10 mm² (42%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 5322-input NAND gate
nor2_17t-5V 3502-input NOR gate
dffrnq_17t-5V 335D flip-flop with reset
mux2_27t-5V 2322-input multiplexer (2x drive)
xor2_17t-5V 2052-input XOR gate
aoi21_17t-5V 194AND-OR-Invert compound gate
oai21_17t-5V 179OR-AND-Invert compound gate
and2_17t-5V 1612-input AND gate
aoi22_17t-5V 160AND-OR-Invert (2x2 inputs)
clkinv_17t-5V 153Clock inverter

Logic density map

113 logic cells, 2,444 transistors 247 logic cells, 2,851 transistors 252 logic cells, 2,761 transistors 235 logic cells, 2,867 transistors 229 logic cells, 2,867 transistors 219 logic cells, 2,818 transistors 1 logic cells, 2,164 transistors 0 logic cells, 147 transistors 204 logic cells, 3,020 transistors 250 logic cells, 3,596 transistors 247 logic cells, 3,190 transistors 217 logic cells, 3,060 transistors 223 logic cells, 3,130 transistors 243 logic cells, 3,159 transistors 12 logic cells, 2,306 transistors 0 logic cells, 153 transistors 199 logic cells, 2,921 transistors 245 logic cells, 3,194 transistors 236 logic cells, 3,031 transistors 219 logic cells, 2,954 transistors 223 logic cells, 3,154 transistors 237 logic cells, 2,940 transistors 4 logic cells, 2,295 transistors 0 logic cells, 153 transistors 30 logic cells, 556 transistors 53 logic cells, 600 transistors 79 logic cells, 653 transistors 60 logic cells, 665 transistors 47 logic cells, 615 transistors 43 logic cells, 602 transistors 0 logic cells, 474 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 287 logic cells 11k 25k 25k 23k 23k 22k <1k 20k 25k 25k 22k 22k 24k 1k 20k 24k 24k 22k 22k 24k <1k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (29k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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