Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

Procedural ASIC

352 · Other digital · 1 × 2 tiles

by Conner Daehler

Layout render of Procedural ASIC

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		14k (18% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		30k (40% of buffer maximum)
Core covered by logic37%
Transistor density
transistors per mm²		253k average, 307k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

animated procedural graphics using XOR and arithmetic patterns

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_connerdaehler_boop
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles1 × 2 at column 4, row 14 of the tile grid
Mux address352
LanguageVerilog
Clock10 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors29,222
Logic cells1,581 + 3,375 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

37%
57%
  • Logic cells 0.04 mm² (37%)
  • Filler and tap cells 0.07 mm² (57%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 2112-input NAND gate
xor2_17t-5V 1852-input XOR gate
nor2_17t-5V 1382-input NOR gate
aoi21_17t-5V 90AND-OR-Invert compound gate
oai21_17t-5V 80OR-AND-Invert compound gate
clkinv_17t-5V 57Clock inverter
xnor2_17t-5V 542-input XNOR gate
and2_17t-5V 532-input AND gate
xor2_27t-5V 442-input XOR gate (2x drive)
xor3_17t-5V 363-input XOR gate

Logic density map

0 logic cells, 2,031 transistors 17 logic cells, 2,157 transistors 55 logic cells, 2,308 transistors 0 logic cells, 880 transistors 54 logic cells, 2,228 transistors 274 logic cells, 3,008 transistors 262 logic cells, 3,410 transistors 72 logic cells, 1,226 transistors 69 logic cells, 2,280 transistors 250 logic cells, 2,880 transistors 267 logic cells, 3,353 transistors 104 logic cells, 1,391 transistors 4 logic cells, 454 transistors 58 logic cells, 632 transistors 73 logic cells, 669 transistors 22 logic cells, 315 transistors Densest SRAM-free 0.1 mm square: 305 logic cells 0 2k 5k 5k 27k 26k 7k 25k 27k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (30k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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