Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

Arctic0 16-bit CPU

356 · RISC-V and CPUs · 1 × 2 tiles

by Einosuke Okazaki

Layout render of Arctic0 16-bit CPU

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		27k (36% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		36k (47% of buffer maximum)
Core covered by logic79%
Transistor density
transistors per mm²		307k average, 322k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

16-bit multi-cycle CPU: SPI flash instructions, SPI SRAM data, UART TX/RX, GPIO and register dump

Source repository no longer public Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_Arctic0
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles1 × 2 at column 6, row 14 of the tile grid
Mux address356
LanguageVerilog
Clock40 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors35,504
Logic cells3,152 + 2,900 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

79%
15%
  • Logic cells 0.09 mm² (79%)
  • Filler and tap cells 0.02 mm² (15%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 4352-input NAND gate
dffrnq_17t-5V 397D flip-flop with reset
dlyb_17t-5V 215Delay buffer
nor2_17t-5V 1912-input NOR gate
aoi21_17t-5V 188AND-OR-Invert compound gate
oai21_17t-5V 161OR-AND-Invert compound gate
mux2_27t-5V 1572-input multiplexer (2x drive)
clkinv_17t-5V 154Clock inverter
aoi22_17t-5V 134AND-OR-Invert (2x2 inputs)
clkbuf_27t-5V 120Clock buffer (2x drive)

Logic density map

315 logic cells, 2,859 transistors 352 logic cells, 3,116 transistors 276 logic cells, 3,206 transistors 127 logic cells, 1,327 transistors 284 logic cells, 2,934 transistors 301 logic cells, 3,305 transistors 267 logic cells, 3,390 transistors 121 logic cells, 1,405 transistors 254 logic cells, 3,270 transistors 238 logic cells, 3,489 transistors 260 logic cells, 3,368 transistors 129 logic cells, 1,366 transistors 82 logic cells, 679 transistors 63 logic cells, 741 transistors 59 logic cells, 737 transistors 24 logic cells, 312 transistors Densest SRAM-free 0.1 mm square: 358 logic cells 31k 35k 28k 28k 30k 27k 25k 24k 26k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (36k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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