Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

Elemental Harmony Game

386 · Games · 2 × 2 tiles

by Aakarshitha Suresh

Layout render of Elemental Harmony Game

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		28k (37% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		44k (58% of buffer maximum)
Core covered by logic60%
Transistor density
transistors per mm²		277k average, 296k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Elemental Harmony is a silicon-based 4 * 4 strategy game, like Tic-Tac-Toe, where players compete against a logic engine to score points by matching elemental patterns across a digital grid.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_elemental_harmony
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles2 × 2 at column 2, row 3 of the tile grid
Mux address386
LanguageVerilog
Clock10 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors64,867
Logic cells6,656 + 7,690 filler and tap cells
Libraries 7t-5V (7k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

60%
35%
  • Logic cells 0.14 mm² (60%)
  • Filler and tap cells 0.08 mm² (35%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 9612-input NAND gate
buf_17t-5V 761Buffer
dlyb_17t-5V 672Delay buffer
nor2_17t-5V 6102-input NOR gate
oai21_17t-5V 557OR-AND-Invert compound gate
clkinv_17t-5V 312Clock inverter
aoi21_17t-5V 270AND-OR-Invert compound gate
aoi22_17t-5V 227AND-OR-Invert (2x2 inputs)
xor2_17t-5V 2252-input XOR gate
dffrnq_17t-5V 185D flip-flop with reset

Logic density map

240 logic cells, 2,527 transistors 279 logic cells, 2,701 transistors 412 logic cells, 2,721 transistors 367 logic cells, 2,721 transistors 361 logic cells, 2,789 transistors 321 logic cells, 3,033 transistors 131 logic cells, 2,419 transistors 0 logic cells, 147 transistors 294 logic cells, 2,807 transistors 328 logic cells, 3,381 transistors 350 logic cells, 2,988 transistors 349 logic cells, 2,782 transistors 315 logic cells, 2,661 transistors 340 logic cells, 3,075 transistors 111 logic cells, 2,483 transistors 0 logic cells, 153 transistors 334 logic cells, 2,863 transistors 348 logic cells, 3,287 transistors 314 logic cells, 3,258 transistors 337 logic cells, 2,922 transistors 344 logic cells, 2,773 transistors 308 logic cells, 3,134 transistors 129 logic cells, 2,499 transistors 0 logic cells, 153 transistors 24 logic cells, 565 transistors 45 logic cells, 750 transistors 54 logic cells, 726 transistors 69 logic cells, 699 transistors 83 logic cells, 624 transistors 67 logic cells, 717 transistors 2 logic cells, 476 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 438 logic cells 24k 28k 41k 37k 36k 32k 13k 29k 33k 35k 35k 31k 34k 11k 33k 35k 31k 34k 34k 31k 13k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (44k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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