Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

AER Reflex Chip - MCP2515 CAN gateway

101 · Communications · 3 × 2 tiles

by khu-haeun

Layout render of AER Reflex Chip - MCP2515 CAN gateway

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		23k (30% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		28k (38% of buffer maximum)
Core covered by logic63%
Transistor density
transistors per mm²		285k average, 305k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Robot-arm reflex core: relays joint commands to CAN via an MCP2515, blocks the stream on a danger trigger and injects a reflex pose. Tuning values (recoil/speed/debounce) hardcoded; rules/threshold/flinch programmable.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size1076 × 325 µm (0.350 mm²)
Macrott_um_reflex_s4
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles3 × 2 at column 6, row 11 of the tile grid
Mux address101
LanguageVerilog
Clock20 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors101,576
Logic cells8,164 + 12,481 filler and tap cells
Libraries 7t-5V (8k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

63%
32%
  • Logic cells 0.22 mm² (63%)
  • Filler and tap cells 0.11 mm² (32%)
  • Other 0.02 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 1,423D flip-flop (1 bit storage)
aoi21_17t-5V 754AND-OR-Invert compound gate
oai21_17t-5V 742OR-AND-Invert compound gate
clkinv_17t-5V 654Clock inverter
nand2_17t-5V 6372-input NAND gate
dlyb_17t-5V 552Delay buffer
nor2_17t-5V 5482-input NOR gate
aoi22_17t-5V 311AND-OR-Invert (2x2 inputs)
clkbuf_27t-5V 249Clock buffer (2x drive)
aoi211_17t-5V 239AND-OR-Invert compound gate

Logic density map

199 logic cells, 2,703 transistors 230 logic cells, 2,757 transistors 245 logic cells, 2,881 transistors 239 logic cells, 2,840 transistors 258 logic cells, 2,899 transistors 237 logic cells, 2,833 transistors 251 logic cells, 3,023 transistors 228 logic cells, 2,872 transistors 247 logic cells, 2,941 transistors 227 logic cells, 2,823 transistors 144 logic cells, 2,046 transistors 225 logic cells, 2,783 transistors 238 logic cells, 2,951 transistors 243 logic cells, 2,901 transistors 275 logic cells, 3,066 transistors 252 logic cells, 3,073 transistors 251 logic cells, 3,059 transistors 255 logic cells, 3,105 transistors 246 logic cells, 3,074 transistors 242 logic cells, 3,096 transistors 239 logic cells, 3,061 transistors 153 logic cells, 2,154 transistors 226 logic cells, 2,865 transistors 215 logic cells, 2,952 transistors 241 logic cells, 3,042 transistors 249 logic cells, 3,105 transistors 253 logic cells, 3,054 transistors 236 logic cells, 2,948 transistors 235 logic cells, 3,018 transistors 247 logic cells, 2,995 transistors 224 logic cells, 2,905 transistors 200 logic cells, 2,943 transistors 130 logic cells, 2,024 transistors 49 logic cells, 567 transistors 57 logic cells, 630 transistors 67 logic cells, 689 transistors 61 logic cells, 667 transistors 62 logic cells, 668 transistors 54 logic cells, 644 transistors 58 logic cells, 627 transistors 52 logic cells, 609 transistors 48 logic cells, 625 transistors 45 logic cells, 616 transistors 31 logic cells, 442 transistors Densest SRAM-free 0.1 mm square: 285 logic cells 20k 23k 24k 24k 26k 24k 25k 23k 25k 23k 14k 22k 24k 24k 27k 25k 25k 25k 25k 24k 24k 15k 23k 21k 24k 25k 25k 24k 23k 25k 22k 20k 13k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (28k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

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