Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

2048 sliding tile puzzle game (VGA)

135 · Games · 3 × 2 tiles

by Uri Shaked

Layout render of 2048 sliding tile puzzle game (VGA)

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		19k (25% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		30k (40% of buffer maximum)
Core covered by logic53%
Transistor density
transistors per mm²		282k average, 348k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Slide numbered tiles on a grid to combine them to create a tile with the number 2048.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size1076 × 325 µm (0.350 mm²)
Macrott_um_2048_vga_game
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles3 × 2 at column 0, row 6 of the tile grid
Mux address135
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors100,459
Logic cells6,736 + 11,639 filler and tap cells
Libraries 7t-5V (7k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

53%
42%
  • Logic cells 0.19 mm² (53%)
  • Filler and tap cells 0.15 mm² (42%)
  • Other 0.02 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 6392-input NAND gate
dffq_17t-5V 454D flip-flop (1 bit storage)
nor2_17t-5V 3682-input NOR gate
buf_27t-5V 353Buffer (2x drive)
oai21_17t-5V 311OR-AND-Invert compound gate
buf_47t-5V 270Buffer (4x drive)
clkinv_17t-5V 263Clock inverter
aoi21_17t-5V 235AND-OR-Invert compound gate
dlyb_17t-5V 220Delay buffer
oai211_17t-5V 194OR-AND-Invert compound gate

Logic density map

166 logic cells, 2,647 transistors 175 logic cells, 2,746 transistors 206 logic cells, 2,708 transistors 214 logic cells, 2,983 transistors 221 logic cells, 2,927 transistors 197 logic cells, 2,993 transistors 195 logic cells, 2,983 transistors 156 logic cells, 2,778 transistors 156 logic cells, 2,701 transistors 183 logic cells, 2,852 transistors 88 logic cells, 2,029 transistors 271 logic cells, 3,394 transistors 277 logic cells, 3,378 transistors 233 logic cells, 2,936 transistors 241 logic cells, 3,048 transistors 279 logic cells, 3,342 transistors 259 logic cells, 3,585 transistors 270 logic cells, 3,154 transistors 200 logic cells, 2,766 transistors 237 logic cells, 3,077 transistors 219 logic cells, 3,017 transistors 112 logic cells, 1,906 transistors 216 logic cells, 2,869 transistors 226 logic cells, 2,943 transistors 233 logic cells, 2,885 transistors 230 logic cells, 3,034 transistors 207 logic cells, 2,960 transistors 195 logic cells, 3,049 transistors 174 logic cells, 2,980 transistors 155 logic cells, 2,780 transistors 122 logic cells, 2,711 transistors 64 logic cells, 2,561 transistors 29 logic cells, 1,706 transistors 14 logic cells, 485 transistors 48 logic cells, 610 transistors 69 logic cells, 700 transistors 55 logic cells, 660 transistors 48 logic cells, 617 transistors 33 logic cells, 560 transistors 43 logic cells, 600 transistors 20 logic cells, 520 transistors 0 logic cells, 474 transistors 0 logic cells, 475 transistors 0 logic cells, 330 transistors Densest SRAM-free 0.1 mm square: 300 logic cells 17k 17k 21k 21k 22k 20k 19k 16k 16k 18k 9k 27k 28k 23k 24k 28k 26k 27k 20k 24k 22k 11k 22k 23k 23k 23k 21k 19k 17k 15k 12k 6k 3k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (30k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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