Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

LEA-128

195 · Security · 2 × 2 tiles

by awayzer JCT

Layout render of LEA-128

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		29k (39% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		38k (50% of buffer maximum)
Core covered by logic76%
Transistor density
transistors per mm²		306k average, 328k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

iterative approach implementation of the LEA128 block cipher

Source repository Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_jct_lea
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles2 × 2 at column 5, row 6 of the tile grid
Mux address195
LanguageVerilog
Clock1 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors71,771
Logic cells6,850 + 6,764 filler and tap cells
Libraries 7t-5V (7k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

76%
19%
  • Logic cells 0.18 mm² (76%)
  • Filler and tap cells 0.04 mm² (19%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 8382-input NAND gate
dffq_17t-5V 776D flip-flop (1 bit storage)
clkinv_17t-5V 546Clock inverter
dlyb_17t-5V 528Delay buffer
aoi22_17t-5V 443AND-OR-Invert (2x2 inputs)
oai21_17t-5V 379OR-AND-Invert compound gate
aoi21_17t-5V 374AND-OR-Invert compound gate
clkbuf_27t-5V 289Clock buffer (2x drive)
nor2_17t-5V 2722-input NOR gate
buf_17t-5V 234Buffer

Logic density map

261 logic cells, 2,905 transistors 281 logic cells, 3,161 transistors 283 logic cells, 3,054 transistors 326 logic cells, 3,030 transistors 281 logic cells, 3,102 transistors 309 logic cells, 2,979 transistors 299 logic cells, 2,901 transistors 3 logic cells, 167 transistors 278 logic cells, 3,062 transistors 318 logic cells, 3,260 transistors 322 logic cells, 3,277 transistors 307 logic cells, 3,603 transistors 326 logic cells, 3,282 transistors 336 logic cells, 3,257 transistors 331 logic cells, 3,091 transistors 7 logic cells, 185 transistors 249 logic cells, 3,061 transistors 268 logic cells, 3,223 transistors 325 logic cells, 3,197 transistors 305 logic cells, 3,245 transistors 314 logic cells, 3,302 transistors 327 logic cells, 3,225 transistors 320 logic cells, 3,249 transistors 7 logic cells, 173 transistors 60 logic cells, 630 transistors 55 logic cells, 625 transistors 66 logic cells, 738 transistors 69 logic cells, 726 transistors 84 logic cells, 697 transistors 69 logic cells, 700 transistors 64 logic cells, 632 transistors 0 logic cells, 32 transistors Densest SRAM-free 0.1 mm square: 383 logic cells 26k 28k 28k 33k 28k 31k 30k 28k 32k 32k 31k 33k 34k 33k 25k 27k 32k 30k 31k 33k 32k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (38k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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