Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

100Mbps Ethernet Accelerator Wrapper

288 · Accelerators · 1 × 2 tiles

by Julia Desmazes

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²
21k (27% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²
26k (34% of buffer maximum)
Core covered by logic63%
Transistor density
transistors per mm²
286k average, 314k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Network connected accelerator wrapper, connected to custom bfloat16 multiplier.

Size347 × 325 µm (0.113 mm²)
Macrott_um_teapot
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles1 × 2 at column 3, row 14 of the tile grid
Mux address288
LanguageVerilog
Clock50 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors33,045
Logic cells2,406 + 4,078 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

63%
30%
  • Logic cells 0.07 mm² (63%)
  • Filler and tap cells 0.03 mm² (30%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 407D flip-flop (1 bit storage)
nand2_17t-5V 2932-input NAND gate
clkinv_17t-5V 136Clock inverter
nor2_17t-5V 1242-input NOR gate
oai21_17t-5V 121OR-AND-Invert compound gate
oai211_17t-5V 94OR-AND-Invert compound gate
aoi22_17t-5V 81AND-OR-Invert (2x2 inputs)
clkbuf_17t-5V 80Clock buffer
dlyb_17t-5V 79Delay buffer
aoi21_17t-5V 78AND-OR-Invert compound gate

Logic density map

146 logic cells, 2,693 transistors 209 logic cells, 2,898 transistors 250 logic cells, 3,175 transistors 103 logic cells, 1,300 transistors 226 logic cells, 2,864 transistors 225 logic cells, 3,017 transistors 225 logic cells, 3,045 transistors 85 logic cells, 1,387 transistors 211 logic cells, 2,884 transistors 237 logic cells, 3,088 transistors 230 logic cells, 3,156 transistors 107 logic cells, 1,294 transistors 40 logic cells, 594 transistors 44 logic cells, 625 transistors 47 logic cells, 711 transistors 21 logic cells, 314 transistors Densest SRAM-free 0.1 mm square: 260 logic cells 15k 21k 25k 23k 22k 22k 21k 24k 23k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (26k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Expresso Ethernet switch has been made on 3 shuttles since Jun 2026. Every version, oldest first, with this one in bold:

  1. Jun 2026 · Tiny Tapeout GF 0.3 Until heat death do us part — 2 × 2 tiles, the heat death of the universe beacon
  2. Jun 2026 · Tiny Tapeout GF 26b 100Mbps Ethernet Accelerator Wrapper — 1 × 2 tiles 100Mbps 3 port Ethernet switch — 2 × 2 tiles
  3. Jul 2026 · wafer.space Run 2 CAFE Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version — ½ × ½ slot

Tiny Tapeout tile Google shuttle wafer.space die

From a Tiny Tapeout tile to a whole die

Expresso Ethernet switch started as a few tiles on Tiny Tapeout GF 0.3 and went on to a die of its own on wafer.space Run 2. When your design outgrows its tiles, a whole die on a wafer.space run is the next step.

Reserve a slot on wafer.space Run 3

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.