Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2

Until heat death do us part

099 · Communications · 2 × 2 tiles

by Julia Desmazes

Layout render of Until heat death do us part

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		17k (22% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		28k (36% of buffer maximum)
Core covered by logic51%
Transistor density
transistors per mm²		276k average, 324k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Counting until the heat death of the universe, broadcasting counter value every second over ethernet.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_coldbrew
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.3
Tiles2 × 2 at column 5, row 11 of the tile grid
Mux address99
LanguageVerilog
Clock50 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors64,761
Logic cells3,961 + 7,642 filler and tap cells
Libraries 7t-5V (4k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

51%
44%
  • Logic cells 0.12 mm² (51%)
  • Filler and tap cells 0.10 mm² (44%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 650D flip-flop (1 bit storage)
nor2_17t-5V 2972-input NOR gate
aoi21_17t-5V 254AND-OR-Invert compound gate
oai21_17t-5V 251OR-AND-Invert compound gate
clkbuf_17t-5V 230Clock buffer
clkinv_17t-5V 212Clock inverter
nand2_17t-5V 2082-input NAND gate
aoi22_17t-5V 191AND-OR-Invert (2x2 inputs)
buf_17t-5V 156Buffer
and2_17t-5V 1322-input AND gate

Logic density map

58 logic cells, 2,292 transistors 133 logic cells, 2,680 transistors 181 logic cells, 2,762 transistors 146 logic cells, 2,655 transistors 162 logic cells, 2,712 transistors 152 logic cells, 2,718 transistors 63 logic cells, 2,374 transistors 0 logic cells, 147 transistors 113 logic cells, 2,537 transistors 237 logic cells, 3,081 transistors 252 logic cells, 3,102 transistors 240 logic cells, 3,308 transistors 258 logic cells, 3,142 transistors 243 logic cells, 3,092 transistors 161 logic cells, 2,801 transistors 0 logic cells, 153 transistors 128 logic cells, 2,664 transistors 239 logic cells, 3,088 transistors 183 logic cells, 2,981 transistors 216 logic cells, 3,169 transistors 221 logic cells, 3,123 transistors 215 logic cells, 3,117 transistors 116 logic cells, 2,664 transistors 0 logic cells, 153 transistors 27 logic cells, 549 transistors 50 logic cells, 648 transistors 34 logic cells, 705 transistors 29 logic cells, 577 transistors 36 logic cells, 588 transistors 61 logic cells, 650 transistors 7 logic cells, 496 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 277 logic cells 6k 13k 18k 15k 16k 15k 6k 11k 24k 25k 24k 26k 24k 16k 13k 24k 18k 22k 22k 21k 12k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (28k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Expresso Ethernet switch has been made on 3 shuttles since Jun 2026. Every version, oldest first, with this one in bold:

  1. Jun 2026 · Tiny Tapeout GF 0.3 Until heat death do us part — 2 × 2 tiles, the heat death of the universe beacon
  2. Jun 2026 · Tiny Tapeout GF 26b 100Mbps 3 port Ethernet switch — 2 × 2 tiles 100Mbps Ethernet Accelerator Wrapper — 1 × 2 tiles
  3. Jul 2026 · wafer.space Run 2 CAFE Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version — ½ × ½ slot

Tiny Tapeout tile Google shuttle wafer.space die

From a Tiny Tapeout tile to a whole die

Expresso Ethernet switch started as a few tiles on Tiny Tapeout GF 26b and went on to a die of its own on wafer.space Run 2. When your design outgrows its tiles, a whole die on a wafer.space run is the next step.

Reserve a slot on wafer.space Run 3

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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