Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

100Mbps 3 port Ethernet switch

199 · Communications · 2 × 2 tiles

by Julia Desmazes

Layout render of 100Mbps 3 port Ethernet switch

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		14k (19% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		31k (40% of buffer maximum)
Core covered by logic52%
Transistor density
transistors per mm²		285k average, 321k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Unmanaged cut-though 3 port 100Mbps ethernet switch

Source repository Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_coffeepot
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles2 × 2 at column 7, row 6 of the tile grid
Mux address199
LanguageVerilog
Clock50 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors66,727
Logic cells3,297 + 5,795 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

52%
43%
  • Logic cells 0.12 mm² (52%)
  • Filler and tap cells 0.10 mm² (43%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 887D flip-flop (1 bit storage)
clkinv_17t-5V 198Clock inverter
buf_47t-5V 187Buffer (4x drive)
mux2_27t-5V 1732-input multiplexer (2x drive)
nand2_17t-5V 1562-input NAND gate
buf_27t-5V 152Buffer (2x drive)
aoi22_17t-5V 118AND-OR-Invert (2x2 inputs)
aoi21_17t-5V 115AND-OR-Invert compound gate
and2_17t-5V 1142-input AND gate
nor2_17t-5V 892-input NOR gate

Logic density map

56 logic cells, 2,499 transistors 104 logic cells, 2,831 transistors 259 logic cells, 3,339 transistors 241 logic cells, 3,339 transistors 235 logic cells, 3,420 transistors 124 logic cells, 2,767 transistors 0 logic cells, 2,129 transistors 0 logic cells, 147 transistors 110 logic cells, 3,085 transistors 193 logic cells, 3,341 transistors 239 logic cells, 3,675 transistors 202 logic cells, 3,083 transistors 160 logic cells, 2,996 transistors 127 logic cells, 2,864 transistors 0 logic cells, 2,219 transistors 0 logic cells, 153 transistors 119 logic cells, 2,796 transistors 260 logic cells, 3,248 transistors 267 logic cells, 3,209 transistors 212 logic cells, 3,453 transistors 185 logic cells, 3,189 transistors 21 logic cells, 2,369 transistors 0 logic cells, 2,218 transistors 0 logic cells, 153 transistors 12 logic cells, 514 transistors 38 logic cells, 790 transistors 56 logic cells, 722 transistors 54 logic cells, 664 transistors 23 logic cells, 531 transistors 0 logic cells, 475 transistors 0 logic cells, 476 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 307 logic cells 6k 10k 26k 24k 23k 12k 0 11k 19k 24k 20k 16k 13k 0 12k 26k 27k 21k 18k 2k 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (31k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Expresso Ethernet switch has been made on 3 shuttles since Jun 2026. Every version, oldest first, with this one in bold:

  1. Jun 2026 · Tiny Tapeout GF 0.3 Until heat death do us part — 2 × 2 tiles, the heat death of the universe beacon
  2. Jun 2026 · Tiny Tapeout GF 26b 100Mbps 3 port Ethernet switch — 2 × 2 tiles 100Mbps Ethernet Accelerator Wrapper — 1 × 2 tiles
  3. Jul 2026 · wafer.space Run 2 CAFE Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version — ½ × ½ slot

Tiny Tapeout tile Google shuttle wafer.space die

From a Tiny Tapeout tile to a whole die

Expresso Ethernet switch started as a few tiles on Tiny Tapeout GF 0.3 and went on to a die of its own on wafer.space Run 2. When your design outgrows its tiles, a whole die on a wafer.space run is the next step.

Reserve a slot on wafer.space Run 3

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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