Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

Programmable Waveform and PWM Generator

450 · Analog and mixed-signal · 2 × 2 tiles

by silicon_nomad

Layout render of Programmable Waveform and PWM Generator

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		15k (20% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		29k (38% of buffer maximum)
Core covered by logic48%
Transistor density
transistors per mm²		271k average, 338k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

UART-programmable waveform and PWM generator. Send samples over UART, stored in 256-byte RAM, played back as 8-bit parallel DAC output or 8 independent PWM channels.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_pattern_gen
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles2 × 2 at column 5, row 3 of the tile grid
Mux address450
LanguageVerilog
Clock10 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors63,487
Logic cells3,560 + 6,743 filler and tap cells
Libraries 7t-5V (4k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

48%
48%
  • Logic cells 0.11 mm² (48%)
  • Filler and tap cells 0.11 mm² (48%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 520D flip-flop (1 bit storage)
nor2_17t-5V 4352-input NOR gate
nand2_17t-5V 3502-input NAND gate
aoi21_17t-5V 347AND-OR-Invert compound gate
dlyb_17t-5V 246Delay buffer
oai21_17t-5V 228OR-AND-Invert compound gate
buf_27t-5V 170Buffer (2x drive)
dffrnq_17t-5V 145D flip-flop with reset
clkinv_17t-5V 117Clock inverter
clkbuf_27t-5V 115Clock buffer (2x drive)

Logic density map

7 logic cells, 2,031 transistors 148 logic cells, 2,657 transistors 214 logic cells, 2,912 transistors 204 logic cells, 2,881 transistors 176 logic cells, 2,767 transistors 26 logic cells, 2,211 transistors 0 logic cells, 2,129 transistors 0 logic cells, 147 transistors 137 logic cells, 2,637 transistors 220 logic cells, 3,138 transistors 252 logic cells, 3,155 transistors 270 logic cells, 3,106 transistors 271 logic cells, 3,408 transistors 109 logic cells, 2,573 transistors 0 logic cells, 2,219 transistors 0 logic cells, 153 transistors 196 logic cells, 2,890 transistors 209 logic cells, 3,152 transistors 237 logic cells, 3,282 transistors 248 logic cells, 3,168 transistors 232 logic cells, 3,406 transistors 126 logic cells, 2,718 transistors 0 logic cells, 2,218 transistors 0 logic cells, 153 transistors 32 logic cells, 561 transistors 58 logic cells, 708 transistors 54 logic cells, 674 transistors 54 logic cells, 695 transistors 50 logic cells, 641 transistors 30 logic cells, 588 transistors 0 logic cells, 476 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 290 logic cells 1k 15k 21k 20k 18k 3k 0 14k 22k 25k 27k 27k 11k 0 20k 21k 24k 25k 23k 13k 0

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (29k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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