Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2

Smerity-Mandelbrot

390 · FPGA · 2 × 2 tiles

by Stephen Merity

Layout render of Smerity-Mandelbrot

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		26k (34% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		32k (42% of buffer maximum)
Core covered by logic65%
Transistor density
transistors per mm²		275k average, 282k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

An interactive fixed-point Mandelbrot iterator with a sequential (bit-serial) multiplier. Tested on iCEBreaker FPGA V1.1a.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size711 × 325 µm (0.231 mm²)
Macrott_um_smerity_mandelbrot
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26b
Tiles2 × 2 at column 0, row 3 of the tile grid
Mux address390
LanguageVerilog
Clock10 MHz
Built withLibreLane 3.0.3, open_pdks 54435919abff
Transistors64,502
Logic cells5,977 + 10,322 filler and tap cells
Libraries 7t-5V (6k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

65%
30%
  • Logic cells 0.15 mm² (65%)
  • Filler and tap cells 0.07 mm² (30%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nor2_17t-5V 9442-input NOR gate
dffq_17t-5V 819D flip-flop (1 bit storage)
oai21_17t-5V 661OR-AND-Invert compound gate
nand2_17t-5V 5672-input NAND gate
aoi21_17t-5V 378AND-OR-Invert compound gate
dlyb_17t-5V 356Delay buffer
clkinv_17t-5V 296Clock inverter
clkbuf_27t-5V 216Clock buffer (2x drive)
xor2_17t-5V 1662-input XOR gate
aoi22_17t-5V 161AND-OR-Invert (2x2 inputs)

Logic density map

253 logic cells, 2,592 transistors 263 logic cells, 2,699 transistors 230 logic cells, 2,718 transistors 258 logic cells, 2,676 transistors 257 logic cells, 2,635 transistors 246 logic cells, 2,804 transistors 258 logic cells, 2,889 transistors 6 logic cells, 171 transistors 269 logic cells, 2,808 transistors 295 logic cells, 2,839 transistors 244 logic cells, 2,819 transistors 292 logic cells, 2,871 transistors 278 logic cells, 2,785 transistors 286 logic cells, 3,162 transistors 265 logic cells, 2,935 transistors 7 logic cells, 190 transistors 262 logic cells, 2,818 transistors 268 logic cells, 2,853 transistors 235 logic cells, 2,858 transistors 282 logic cells, 2,864 transistors 249 logic cells, 2,818 transistors 262 logic cells, 3,152 transistors 252 logic cells, 2,943 transistors 7 logic cells, 171 transistors 52 logic cells, 561 transistors 64 logic cells, 648 transistors 80 logic cells, 655 transistors 66 logic cells, 670 transistors 68 logic cells, 630 transistors 62 logic cells, 619 transistors 61 logic cells, 612 transistors 0 logic cells, 37 transistors Densest SRAM-free 0.1 mm square: 317 logic cells 25k 26k 23k 26k 26k 25k 26k 27k 29k 24k 29k 28k 29k 26k 26k 27k 23k 28k 25k 26k 25k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (32k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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