Tiny Tapeout GF 26b · Die T26B on wafer.space Run 2
Asynchronous-AER Spike Router (4-phase REQ/ACK, 16-entry routing table, GF180)
096 · Other digital · 1 × 2 tiles
by Prof. Santhosh Sivasubramani, IIT Delhi
Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Core average logic cells per mm² | 14k (18% of buffer maximum) |
|---|---|
| Densest 0.1 mm square logic cells per mm² | 23k (30% of buffer maximum) |
| Core covered by logic | 49% |
| Transistor density transistors per mm² | 272k average, 344k in the 0.1 mm square with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
GF180mcuD synchronous implementation of a 4-input / 4-output AER (address-event-representation) spike router. Time-multiplexed AER input and output buses each carry one event at a time as a 2-bit channel tag plus 6-bit address. Each incoming event is captured using a double-flop-synchronised 4-phase bundled-data REQ/ACK handshake, looked up in a 16-entry {dst_ch, dst_addr} routing table (or bypassed to pass through unchanged), queued in a 4-deep FIFO, and emitted out the output port with another 4-phase REQ/ACK handshake. Drops on FIFO overflow are counted in a 16-bit saturating drop counter with a sticky overflow_ever bit. Per-input 8-bit saturating event counters and IN_LAST / OUT_LAST debug latches are readable over SPI. 25 MHz signoff clock.
Source repository no longer public Its page on Tiny TapeoutBuy a chip and board
| Size | 347 × 325 µm (0.113 mm²) |
|---|---|
| Macro | tt_um_santhosh_aer_router_gf |
| Files | documentation · licence · layout and netlist in Tiny Tapeout GF 26b |
| Tiles | 1 × 2 at column 4, row 10 of the tile grid |
| Mux address | 96 |
| Language | Verilog |
| Clock | 25 MHz |
| Built with | LibreLane 3.0.3, open_pdks 54435919abff |
| Transistors | 31,441 |
| Logic cells | 1,594 + 3,607 filler and tap cells |
| Libraries | 7t-5V (2k) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Where the area went
How this project's area splits between logic cells, filler and tap cells and other.
- Logic cells 0.06 mm² (49%)
- Filler and tap cells 0.05 mm² (44%)
- Other 0.01 mm² (7%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| dffrnq_1 | 7t-5V | 299 | D flip-flop with reset |
| mux2_2 | 7t-5V | 226 | 2-input multiplexer (2x drive) |
| aoi22_1 | 7t-5V | 146 | AND-OR-Invert (2x2 inputs) |
| dlyb_1 | 7t-5V | 99 | Delay buffer |
| nand2_1 | 7t-5V | 90 | 2-input NAND gate |
| clkbuf_2 | 7t-5V | 68 | Clock buffer (2x drive) |
| buf_2 | 7t-5V | 64 | Buffer (2x drive) |
| nor2_1 | 7t-5V | 52 | 2-input NOR gate |
| aoi21_1 | 7t-5V | 48 | AND-OR-Invert compound gate |
| oai21_1 | 7t-5V | 33 | OR-AND-Invert compound gate |
Logic density map
Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (23k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.