Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 10k
(14% of buffer maximum) over the 5.02 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 5k
over all 9.61 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 19k (25% of buffer maximum) |
| Core covered by logic | 29% |
| Transistor density transistors per mm² | 204k average, 265k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
| Die | 3.93 × 2.53 mm (9.9 mm²) |
|---|---|
| Core area | 5.02 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 9.61 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot C1 |
| Bond pads | 72 |
| Probe pads | 16 |
| Transistors | 1,025,108 |
| Logic cells | 52,199 + 100,188 filler and tap cells |
| Libraries | 7t-5V (52k) |
| SRAM | 6 macros, 20,480 bits |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.5.5 or 1.5.6 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 2081f9bda695.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_COMMIT 140b0494c666). |
| Chip-on-board | Selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-15, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | 40 custom transistors |
|---|---|
| 5 V | 7t-5V standard cells, fd SRAM, 104 custom transistors |
| 6 V | 44 custom transistors |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MIM capacitors | 9
(900 µm², between Metal4 and Metal5)
all in reused simple_por |
| High-resistance poly resistors | 88
(2,200 µm²)
all in reused simple_por |
| Unsalicided poly resistors | 13 (376 µm²) |
| I/O library | gf180mcu_fd_io (758 cells) |
Where the area went
How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.
- Logic cells 1.44 mm² (14%)
- SRAM 1.13 mm² (11%)
- Filler and tap cells 1.52 mm² (15%)
- Other 0.93 mm² (9%)
- Pad ring 4.92 mm² (50%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| buf_2 | 7t-5V | 12,985 | Buffer (2x drive) |
| nand2_1 | 7t-5V | 5,571 | 2-input NAND gate |
| dffq_1 | 7t-5V | 5,348 | D flip-flop (1 bit storage) |
| oai21_1 | 7t-5V | 3,778 | OR-AND-Invert compound gate |
| aoi21_1 | 7t-5V | 3,001 | AND-OR-Invert compound gate |
| nor2_1 | 7t-5V | 2,756 | 2-input NOR gate |
| clkbuf_1 | 7t-5V | 1,789 | Clock buffer |
| aoi22_1 | 7t-5V | 1,752 | AND-OR-Invert (2x2 inputs) |
| clkinv_1 | 7t-5V | 1,347 | Clock inverter |
| dffrnq_1 | 7t-5V | 1,191 | D flip-flop with reset |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (19k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_fd_ip_sram__sram256x8m8wm1 | 2 | 2,048 |
| gf180mcu_fd_ip_sram__sram512x8m8wm1 | 4 | 4,096 |
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. CAB1 was accepted on this check, and has been checked again since with newer rules.
All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-15.
Every step, and the latest re-run
| Step | Accepted on check 557, 2026-07-15, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 | Latest re-run check 742, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.CheckPadMask | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | advisory warning | advisory warning |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 505 | 505 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.