wafer.space Run 2

BTX

BTX1 · Accelerators · 1 × 1 slot

Layout render of BTX

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		20k (26% of buffer maximum)
over the 12.90 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		13k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		25k (33% of buffer maximum)
Core covered by logic47%
Transistor density
transistors per mm²		314k average, 322k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Path-tracing accelerator chip

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot A5 BTX1 on the reticle
Bond pads74
Transistors4,046,673
Logic cells252,619 + 505,451 filler and tap cells
Libraries AS 7t-3.3V (253k)
SRAM19 macros, 71,680 bits

Submission

LicenceCERN-OHL-S-2.0 declared
No public repository
Chip-on-boardSelected at submission
PrecheckPassed the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.1 (from its image)
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells, ocd SRAM
Gate oxidesThin only (3.3 V) in the design itself
the pad ring adds thick-oxide (6 V) transistors
I/O librarygf180mcu_fd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

30%
9%
23%
36%
  • Logic cells 6.05 mm² (30%)
  • SRAM 1.76 mm² (9%)
  • Filler and tap cells 4.73 mm² (23%)
  • Other 0.37 mm² (2%)
  • Pad ring 7.22 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_2AS 7t-3.3V 24,6792-input NAND gate (2x drive)
buff_2AS 7t-3.3V 23,530Buffer (2x drive)
xnor2_2AS 7t-3.3V 22,9072-input XNOR gate (2x drive)
oai21_2AS 7t-3.3V 17,858OR-AND-Invert compound gate (2x drive)
ao22_2AS 7t-3.3V 14,584AND-OR compound gate (2x2 inputs, 2x drive)
aoi21_2AS 7t-3.3V 13,437AND-OR-Invert compound gate (2x drive)
nand3_2AS 7t-3.3V 11,7273-input NAND gate (2x drive)
and2_2AS 7t-3.3V 11,2612-input AND gate (2x drive)
xor2_2AS 7t-3.3V 10,0082-input XOR gate (2x drive)
dfxtp_2AS 7t-3.3V 9,378D flip-flop (1 bit storage, 2x drive)

Logic density map

1,090 logic cells, 83,853 transistors, 22% SRAM 7,580 logic cells, 162,495 transistors, 20% SRAM 13,140 logic cells, 173,744 transistors 6,561 logic cells, 87,672 transistors 3,738 logic cells, 179,128 transistors, 33% SRAM 16,929 logic cells, 326,373 transistors, 22% SRAM 23,571 logic cells, 312,482 transistors 11,748 logic cells, 157,937 transistors 5,613 logic cells, 171,156 transistors, 26% SRAM 22,584 logic cells, 330,562 transistors 23,163 logic cells, 311,882 transistors 11,486 logic cells, 160,158 transistors 6,296 logic cells, 167,793 transistors, 25% SRAM 23,921 logic cells, 327,234 transistors 24,428 logic cells, 319,893 transistors 7,242 logic cells, 151,314 transistors, 17% SRAM 4,137 logic cells, 82,868 transistors, 8% SRAM 16,565 logic cells, 217,206 transistors 15,917 logic cells, 211,767 transistors 6,910 logic cells, 110,310 transistors, 4% SRAM 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 Densest SRAM-free mm²: 24,790 logic cells 1k 8k 13k 7k 4k 17k 24k 12k 6k 23k 23k 11k 6k 24k 24k 7k 4k 17k 16k 7k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (25k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_ocd_ip_sram__sram256x8m8wm13 2,048
gf180mcu_ocd_ip_sram__sram512x8m8wm116 4,096

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. BTX1 was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-14.

Every step, and the latest re-run
StepAccepted on
check 492, 2026-07-14, initial, gf180mcu-precheck 1.7.1 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 791, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.CheckPadMaskpassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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