TinyQV - RISC-V SoC with HDMI output

TQVD · RISC-V and CPUs · ½ × ½ slot

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core logic cells per mm²	14k (18% of buffer maximum) over the 1.73 mm² core: what the design itself packed
Inside the seal ring logic cells per mm²	5k over all 4.68 mm² of the slot, pad ring included
Core covered by logic	37%
Transistor density transistors per mm²	354k average

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

This version of TinyQV uses the new 3v3 standard cell library, 3v3 SRAM macros and the split voltage pads. Apart from that it is similar to the Run 1 TinyQV, but with additional scratch RAM, new HDMI/VGA text mode output support and a single 8-bit DAC.

Source repository

Die	1.94 × 2.53 mm (4.9 mm²)
Core area	1.73 mm² inside the pad ring as set in the design's own layout settings
Inside the seal ring	4.68 mm² (the die less its 26 µm seal ring)
Placements	1 on the reticle, in slot H1
Bond pads	56
Transistors	612,804
Logic cells	23,689 + 40,036 filler and tap cells
Libraries	AS 7t-3.3V (24k)
SRAM	5 macros, 32,768 bits

Submission

Licence	Apache-2.0 declared Repository: Apache-2.0 in LICENSE — agrees
Template	wafer-space/gf180mcu-project-template 1.5.8
How it was checked	Commit and PDK pin The licence and template were read from the repository at commit 1ac951fb0fd3.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT f6eeac7dad08).
Chip-on-board	Selected at submission
Precheck	Passed the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.2 (from its image) Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 V	AS 7t-3.3V standard cells, ocd SRAM
Gate oxides	Thin only (3.3 V) in the design itself the pad ring adds thick-oxide (5 V, 6 V) transistors
High-resistance poly resistors	27 (2,700 µm²) all in reused r2r
I/O library	gf180mcu_ocd_io (424 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

13%

65%

Logic cells 0.64 mm² (13%)
SRAM 0.66 mm² (13%)
Filler and tap cells 0.35 mm² (7%)
Other 0.08 mm² (2%)
Pad ring 3.18 mm² (65%)

Most used cells

The ten standard cells this design uses most.

Cell	Library	Instances	What it does
dlybuff_2	AS 7t-3.3V	3,549	Delay buffer (2x drive)
dfxtp_2	AS 7t-3.3V	2,993	D flip-flop (1 bit storage, 2x drive)
mux2_2	AS 7t-3.3V	2,395	2-input multiplexer (2x drive)
buff_2	AS 7t-3.3V	2,238	Buffer (2x drive)
and2_2	AS 7t-3.3V	2,019	2-input AND gate (2x drive)
ao22_2	AS 7t-3.3V	996	AND-OR compound gate (2x2 inputs, 2x drive)
nor2_2	AS 7t-3.3V	844	2-input NOR gate (2x drive)
ao211_2	AS 7t-3.3V	834	AND-OR compound gate (2+1+1 inputs, 2x drive)
nand2_2	AS 7t-3.3V	814	2-input NAND gate (2x drive)
ao31_2	AS 7t-3.3V	778	AND-OR compound gate (3+1 inputs, 2x drive)

Logic density map

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

Macro	Count	Bits each
gf180mcu_ocd_ip_sram__sram1024x8m8wm1	3	8,192
gf180mcu_ocd_ip_sram__sram512x8m8wm1	2	4,096

TinyQV RISC-V SoC has been made on 11 shuttles since Apr 2024. Every version, oldest first, with this one in bold:

Apr 2024 · Tiny Tapeout 6 TinyQV RISC-V SoC — 2 × 2 tiles
Nov 2024 · Tiny Tapeout IHP 0.2 TinyQV RISC-V SoC — 2 × 2 tiles
Mar 2025 · Tiny Tapeout IHP 25a TinyQV RISC-V SoC — 3 × 2 tiles
Sep 2025 · Tiny Tapeout IHP 25b TinyQV - Crowdsourced RISC-V SoC — 5 × 4 tiles, with the peripherals of Tiny Tapeout's RISC-V competition
Sep 2025 · Tiny Tapeout SKY 25a TinyQV 'Asteroids' - Crowdsourced RISC-V SoC — 8 × 4 tiles, 'Asteroids', with crowdsourced peripherals TinyQV 'Berzerk' - Crowdsourced RISC-V SoC — 4 × 4 tiles, 'Berzerk', with crowdsourced peripherals
Nov 2025 · Tiny Tapeout SKY 25b TinyQV RISC-V SoC — 3 × 2 tiles
Nov 2025 · Tiny Tapeout GF 0.1 TinyQV RISC-V SoC — in a shared block
Nov 2025 · Tiny Tapeout GF 0.2 TinyQV RISC-V SoC — 3 × 4 tiles
Dec 2025 · wafer.space Run 1 TQVA TinyQV - Crowdsourced RISC-V SoC — ½ × ½ slot TQVB TinyQV - Crowdsourced RISC-V SoC (0.5x1) — ½ × 1 slot TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5) — 1 × ½ slot
Jun 2026 · Tiny Tapeout GF 0.3 TinyQV RISC-V SoC — 4 × 2 tiles
Jul 2026 · wafer.space Run 2 TQVD TinyQV - RISC-V SoC with HDMI output — ½ × ½ slot, 3.3 V standard cells and SRAM, HDMI output TQVA TinyQV - Crowdsourced RISC-V SoC — ½ × ½ slot TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5) — 1 × ½ slot TQVE TinyQV - RISC-V SoC with experimental pad setup — ½ × ½ slot, 3.3 V, with an experimental pad setup

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made on	Slot	Library	Gate oxides	Logic cells	Per mm² of core	Densest	SRAM
wafer.space Run 1 · TQVA	½ × ½	7t-5V	5 V/6 V only	35,711	21k	23k	1 macro
wafer.space Run 1 · TQVB	½ × 1	7t-5V	5 V/6 V only	35,416	8k	24k	1 macro
wafer.space Run 1 · TQVC	1 × ½	7t-5V	5 V/6 V only	36,116	7k	16k	1 macro
wafer.space Run 2 · TQVA the same logic cells and transistors as TQVA on wafer.space Run 1	½ × ½	7t-5V	5 V/6 V only	35,711	21k	23k	1 macro
wafer.space Run 2 · TQVC the same logic cells and transistors as TQVC on wafer.space Run 1	1 × ½	7t-5V	5 V/6 V only	36,116	7k	16k	1 macro
wafer.space Run 2 · TQVD	½ × ½	AS 7t-3.3V	3.3 V only	23,689	14k	1k	5 macros
wafer.space Run 2 · TQVE	½ × ½	AS 7t-3.3V	3.3 V only	24,213	14k	16k	10 macros

From Tiny Tapeout tiles to a die of its own

TinyQV RISC-V SoC began as tiles on Tiny Tapeout 6, and now has dies of its own on wafer.space Run 1 and wafer.space Run 2.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. TQVD was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-14.

Every step, and the latest re-run

Step	Accepted on check 522, 2026-07-14, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1	Latest re-run check 720, 2026-08-02, retry, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayout	passed	passed
KLayout.CheckTopLevel	passed	passed
KLayout.CheckSize	passed	passed
KLayout.CheckPadMask	passed	passed
KLayout.GenerateID	passed	passed
KLayout.Render	passed	passed
KLayout.Density	passed	passed
Checker.KLayoutDensity	passed	passed
KLayout.ZeroAreaPolygons	passed	passed
Checker.KLayoutZeroAreaPolygons	passed	passed
KLayout.Antenna	passed	passed
Checker.KLayoutAntenna	passed	passed
Magic.DRC	passed	passed
Checker.MagicDRC	passed	passed
KLayout.DRC	passed	passed
Checker.KLayoutDRC	passed	passed
KLayout.WriteLayout	passed	passed
KLayout DRC errors	0	0
Magic DRC errors (advisory)	0	0
Files	steps · log (gzip)	steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

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