TinyQV - RISC-V SoC with experimental pad setup
TQVE · RISC-V and CPUs · ½ × ½ slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 14k
(18% of buffer maximum) over the 1.74 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 5k
over all 4.68 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 16k (21% of buffer maximum) |
| Core covered by logic | 40% |
| Transistor density transistors per mm² | 568k average, 248k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
This version of TinyQV uses the new 3v3 standard cell library, 3v3 SRAM macros and a single line of pads to allow more area with fewer pins. The extra space is used for 9.5kB of scratch RAM. It also has a USB CDC peripheral which should allow serial comms without an external UART.
| Die | 1.94 × 2.53 mm (4.9 mm²) |
|---|---|
| Core area | 1.74 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 4.68 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot H2 |
| Bond pads | 17 |
| Transistors | 986,961 |
| Logic cells | 24,213 + 70,319 filler and tap cells |
| Libraries | AS 7t-3.3V (24k) |
| SRAM | 10 macros, 77,824 bits |
Submission
| Licence | Apache-2.0 declared
No public repository |
|---|---|
| Chip-on-board | Not selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | AS 7t-3.3V standard cells, ocd SRAM |
|---|---|
| Gate oxides | Thin only (3.3 V) in the design itself the pad ring adds thick-oxide (6 V) transistors |
| I/O library | gf180mcu_fd_io (107 cells) |
Where the area went
How this design's area splits between logic cells, SRAM, filler and tap cells and pad ring.
- Logic cells 0.69 mm² (11%)
- SRAM 1.50 mm² (24%)
- Filler and tap cells 1.00 mm² (16%)
- Pad ring 3.17 mm² (50%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| dlybuff_2 | AS 7t-3.3V | 3,919 | Delay buffer (2x drive) |
| dfxtp_2 | AS 7t-3.3V | 2,959 | D flip-flop (1 bit storage, 2x drive) |
| mux2_2 | AS 7t-3.3V | 2,935 | 2-input multiplexer (2x drive) |
| and2_2 | AS 7t-3.3V | 2,230 | 2-input AND gate (2x drive) |
| buff_2 | AS 7t-3.3V | 1,651 | Buffer (2x drive) |
| ao22_2 | AS 7t-3.3V | 863 | AND-OR compound gate (2x2 inputs, 2x drive) |
| nor2_2 | AS 7t-3.3V | 859 | 2-input NOR gate (2x drive) |
| nand2_2 | AS 7t-3.3V | 738 | 2-input NAND gate (2x drive) |
| xnor2_2 | AS 7t-3.3V | 705 | 2-input XNOR gate (2x drive) |
| inv_2 | AS 7t-3.3V | 691 | Inverter (2x drive) |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (16k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_ocd_ip_sram__sram1024x8m8wm1 | 9 | 8,192 |
| gf180mcu_ocd_ip_sram__sram512x8m8wm1 | 1 | 4,096 |
How this design grew
TinyQV RISC-V SoC has been made on 11 shuttles since Apr 2024. Every version, oldest first, with this one in bold:
- Apr 2024 · Tiny Tapeout 6 TinyQV RISC-V SoC — 2 × 2 tiles
- Nov 2024 · Tiny Tapeout IHP 0.2 TinyQV RISC-V SoC — 2 × 2 tiles
- Mar 2025 · Tiny Tapeout IHP 25a TinyQV RISC-V SoC — 3 × 2 tiles
- Sep 2025 · Tiny Tapeout IHP 25b TinyQV - Crowdsourced RISC-V SoC — 5 × 4 tiles, with the peripherals of Tiny Tapeout's RISC-V competition
- Sep 2025 · Tiny Tapeout SKY 25a TinyQV 'Asteroids' - Crowdsourced RISC-V SoC — 8 × 4 tiles, 'Asteroids', with crowdsourced peripherals TinyQV 'Berzerk' - Crowdsourced RISC-V SoC — 4 × 4 tiles, 'Berzerk', with crowdsourced peripherals
- Nov 2025 · Tiny Tapeout SKY 25b TinyQV RISC-V SoC — 3 × 2 tiles
- Nov 2025 · Tiny Tapeout GF 0.1 TinyQV RISC-V SoC — in a shared block
- Nov 2025 · Tiny Tapeout GF 0.2 TinyQV RISC-V SoC — 3 × 4 tiles
- Dec 2025 · wafer.space Run 1 TQVA TinyQV - Crowdsourced RISC-V SoC — ½ × ½ slot TQVB TinyQV - Crowdsourced RISC-V SoC (0.5x1) — ½ × 1 slot TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5) — 1 × ½ slot
- Jun 2026 · Tiny Tapeout GF 0.3 TinyQV RISC-V SoC — 4 × 2 tiles
- Jul 2026 · wafer.space Run 2 TQVE TinyQV - RISC-V SoC with experimental pad setup — ½ × ½ slot, 3.3 V, with an experimental pad setup TQVA TinyQV - Crowdsourced RISC-V SoC — ½ × ½ slot TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5) — 1 × ½ slot TQVD TinyQV - RISC-V SoC with HDMI output — ½ × ½ slot, 3.3 V standard cells and SRAM, HDMI output
Tiny Tapeout tile Google shuttle wafer.space die
Its dies compared
Every die of this design measured here, oldest first, with this one in bold.
| Made on | Slot | Library | Gate oxides | Logic cells | Per mm² of core | Densest | SRAM |
|---|---|---|---|---|---|---|---|
| wafer.space Run 1 · TQVA | ½ × ½ | 7t-5V | 5 V/6 V only | 35,711 | 21k | 23k | 1 macro |
| wafer.space Run 1 · TQVB | ½ × 1 | 7t-5V | 5 V/6 V only | 35,416 | 8k | 24k | 1 macro |
| wafer.space Run 1 · TQVC | 1 × ½ | 7t-5V | 5 V/6 V only | 36,116 | 7k | 16k | 1 macro |
| wafer.space Run 2 · TQVA the same logic cells and transistors as TQVA on wafer.space Run 1 |
½ × ½ | 7t-5V | 5 V/6 V only | 35,711 | 21k | 23k | 1 macro |
| wafer.space Run 2 · TQVC the same logic cells and transistors as TQVC on wafer.space Run 1 |
1 × ½ | 7t-5V | 5 V/6 V only | 36,116 | 7k | 16k | 1 macro |
| wafer.space Run 2 · TQVD | ½ × ½ | AS 7t-3.3V | 3.3 V only | 23,689 | 14k | 1k | 5 macros |
| wafer.space Run 2 · TQVE | ½ × ½ | AS 7t-3.3V | 3.3 V only | 24,213 | 14k | 16k | 10 macros |
From Tiny Tapeout tiles to a die of its own
TinyQV RISC-V SoC began as tiles on Tiny Tapeout 6, and now has dies of its own on wafer.space Run 1 and wafer.space Run 2.
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. TQVE was accepted on this check, and has been checked again since with newer rules.
All 16 steps passed, with 0 KLayout DRC errors, on 2026-07-14.
Every step, and the latest re-run
| Step | Accepted on check 517, 2026-07-14, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 | Latest re-run check 713, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.