TinyQV - Crowdsourced RISC-V SoC (0.5x1)

TQVB · RISC-V and CPUs · ½ × 1 slot

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core logic cells per mm²	8k (10% of buffer maximum) over the 4.46 mm² core: what the design itself packed
Inside the seal ring logic cells per mm²	4k over all 9.57 mm² of the slot, pad ring included
Densest mm² logic cells per mm²	24k (31% of buffer maximum)
Core covered by logic	18%
Transistor density transistors per mm²	244k average, 276k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

A Risc-V RV32EC SoC with peripherals from the Tiny Tapeout Risc-V competition. This version uses a half width slot (but is otherwise identical to the quarter size version)

Source repository Die photograph

Die	1.94 × 5.12 mm (9.9 mm²)
Core area	4.46 mm² inside the pad ring as set in the design's own layout settings
Inside the seal ring	9.57 mm² (the die less its 26 µm seal ring)
Placements	1 on the reticle, in slot H2
Bond pads	72
Transistors	1,089,232
Logic cells	35,416 + 123,968 filler and tap cells
Libraries	7t-5V (35k)
SRAM	1 macro, 4,096 bits

Submission

Licence	Apache-2.0 declared Repository: Apache-2.0 in LICENSE — agrees
Template	wafer-space/gf180mcu-project-template 1.3.3 or 1.3.4
How it was checked	Commit and PDK pin The licence and template were read from the repository at commit 2c8630bce07f.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.5).
Chip-on-board	Not selected at submission
Precheck	Passed the check it was accepted on, 2025-12-17, gf180mcu-precheck 1.5.5 (from its image) Passed latest re-run, 2026-07-30, gf180mcu-precheck 1.7.3 step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V	7t-5V standard cells, fd SRAM
Gate oxides	Thick only (5 V/6 V) in the design itself
I/O library	gf180mcu_fd_io (834 cells), gf180mcu_ws_io (16 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

34%

55%

Logic cells 0.80 mm² (8%)
SRAM 0.21 mm² (2%)
Filler and tap cells 3.42 mm² (34%)
Other 0.03 mm² (<1%)
Pad ring 5.47 mm² (55%)

Most used cells

The ten standard cells this design uses most.

Cell	Library	Instances	What it does
nand2_1	7t-5V	8,753	2-input NAND gate
clkinv_1	7t-5V	3,208	Clock inverter
oai21_1	7t-5V	3,174	OR-AND-Invert compound gate
dffq_1	7t-5V	2,991	D flip-flop (1 bit storage)
buf_2	7t-5V	1,951	Buffer (2x drive)
nand3_1	7t-5V	1,636	3-input NAND gate
nor2_1	7t-5V	1,361	2-input NOR gate
aoi21_1	7t-5V	1,257	AND-OR-Invert compound gate
buf_1	7t-5V	988	Buffer
latq_1	7t-5V	955	Latch (level-sensitive)

Logic density map

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (24k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

Macro	Count	Bits each
gf180mcu_fd_ip_sram__sram512x8m8wm1	1	4,096

TinyQV RISC-V SoC has been made on 11 shuttles since Apr 2024. Every version, oldest first, with this one in bold:

Apr 2024 · Tiny Tapeout 6 TinyQV RISC-V SoC — 2 × 2 tiles
Nov 2024 · Tiny Tapeout IHP 0.2 TinyQV RISC-V SoC — 2 × 2 tiles
Mar 2025 · Tiny Tapeout IHP 25a TinyQV RISC-V SoC — 3 × 2 tiles
Sep 2025 · Tiny Tapeout IHP 25b TinyQV - Crowdsourced RISC-V SoC — 5 × 4 tiles, with the peripherals of Tiny Tapeout's RISC-V competition
Sep 2025 · Tiny Tapeout SKY 25a TinyQV 'Asteroids' - Crowdsourced RISC-V SoC — 8 × 4 tiles, 'Asteroids', with crowdsourced peripherals TinyQV 'Berzerk' - Crowdsourced RISC-V SoC — 4 × 4 tiles, 'Berzerk', with crowdsourced peripherals
Nov 2025 · Tiny Tapeout SKY 25b TinyQV RISC-V SoC — 3 × 2 tiles
Nov 2025 · Tiny Tapeout GF 0.1 TinyQV RISC-V SoC — in a shared block
Nov 2025 · Tiny Tapeout GF 0.2 TinyQV RISC-V SoC — 3 × 4 tiles
Dec 2025 · wafer.space Run 1 TQVB TinyQV - Crowdsourced RISC-V SoC (0.5x1) — ½ × 1 slot TQVA TinyQV - Crowdsourced RISC-V SoC — ½ × ½ slot TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5) — 1 × ½ slot
Jun 2026 · Tiny Tapeout GF 0.3 TinyQV RISC-V SoC — 4 × 2 tiles
Jul 2026 · wafer.space Run 2 TQVA TinyQV - Crowdsourced RISC-V SoC — ½ × ½ slot TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5) — 1 × ½ slot TQVD TinyQV - RISC-V SoC with HDMI output — ½ × ½ slot, 3.3 V standard cells and SRAM, HDMI output TQVE TinyQV - RISC-V SoC with experimental pad setup — ½ × ½ slot, 3.3 V, with an experimental pad setup

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made on	Slot	Library	Gate oxides	Logic cells	Per mm² of core	Densest	SRAM
wafer.space Run 1 · TQVA	½ × ½	7t-5V	5 V/6 V only	35,711	21k	23k	1 macro
wafer.space Run 1 · TQVB	½ × 1	7t-5V	5 V/6 V only	35,416	8k	24k	1 macro
wafer.space Run 1 · TQVC	1 × ½	7t-5V	5 V/6 V only	36,116	7k	16k	1 macro
wafer.space Run 2 · TQVA the same logic cells and transistors as TQVA on wafer.space Run 1	½ × ½	7t-5V	5 V/6 V only	35,711	21k	23k	1 macro
wafer.space Run 2 · TQVC the same logic cells and transistors as TQVC on wafer.space Run 1	1 × ½	7t-5V	5 V/6 V only	36,116	7k	16k	1 macro
wafer.space Run 2 · TQVD	½ × ½	AS 7t-3.3V	3.3 V only	23,689	14k	1k	5 macros
wafer.space Run 2 · TQVE	½ × ½	AS 7t-3.3V	3.3 V only	24,213	14k	16k	10 macros

From Tiny Tapeout tiles to a die of its own

TinyQV RISC-V SoC began as tiles on Tiny Tapeout 6, and now has dies of its own on wafer.space Run 1 and wafer.space Run 2.

The fabricated die

Die photograph of TinyQV - Crowdsourced RISC-V SoC (0.5x1) by InfoSecDJ

InfoSecDJ's zoomable viewer · Larger image · full resolution (very large file) · all photographs

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. TQVB was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-17.

Every step, and the latest re-run

Step	Accepted on check 150, 2025-12-17, initial, gf180mcu-precheck 1.5.5 (from its image) PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e	Latest re-run check 699, 2026-07-30, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayout	passed	passed
KLayout.CheckTopLevel	passed	passed
KLayout.CheckSize	passed	passed
KLayout.GenerateID	passed	passed
KLayout.Render	not in this flow	passed
KLayout.Density	passed	passed
Checker.KLayoutDensity	passed	passed
KLayout.ZeroAreaPolygons	passed	passed
Checker.KLayoutZeroAreaPolygons	passed	passed
KLayout.Antenna	passed	passed
Checker.KLayoutAntenna	passed	passed
Magic.DRC	passed	passed
Checker.MagicDRC	passed	passed
KLayout.DRC	passed	passed
Checker.KLayoutDRC	passed	passed
KLayout.WriteLayout	passed	passed
KLayout DRC errors	0	0
Magic DRC errors (advisory)	0	0
Files	steps · log (gzip)	steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

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