wafer.space Run 2

GF180MCU Peripherals

SCUP · Other digital · 1 × 1 slot

Layout render of GF180MCU Peripherals

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		19k (24% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		12k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		34k (45% of buffer maximum)
Core covered by logic53%
Transistor density
transistors per mm²		293k average, 351k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

This open-source chip demonstrates an RMII Ethernet MAC, an SDcard reader, an SDRAM controller, and several different configurations of PLLs.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot C4 SCUP on the reticle
Bond pads74
Transistors3,785,178
Logic cells239,123 + 684,932 filler and tap cells
Libraries AS 7t-3.3V (239k)
SRAMNo SRAM

Submission

LicenceGPL-3.0-or-later declared
Repository: GPL-3.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.5.3
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit bee7cb698112.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT 019cf7a3e0de).
Chip-on-boardSelected at submission
PrecheckPassed the check it was accepted on, 2026-07-12, gf180mcu-precheck 1.7.1 (from its image)
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells
Gate oxidesThin only (3.3 V) in the design itself
the pad ring adds thick-oxide (5 V, 6 V) transistors
I/O librarygf180mcu_ocd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and pad ring.

34%
30%
36%
  • Logic cells 6.82 mm² (34%)
  • Filler and tap cells 6.08 mm² (30%)
  • Other 0.02 mm² (<1%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
buff_2AS 7t-3.3V 54,291Buffer (2x drive)
dlybuff_2AS 7t-3.3V 34,397Delay buffer (2x drive)
mux2_2AS 7t-3.3V 32,5312-input multiplexer (2x drive)
dfxtp_2AS 7t-3.3V 31,637D flip-flop (1 bit storage, 2x drive)
clkbuff_12AS 7t-3.3V 9,667Clock buffer (12x drive)
aoi21b_2AS 7t-3.3V 8,442AND-OR-Invert, one input inverted (2x drive)
nor2_2AS 7t-3.3V 8,3522-input NOR gate (2x drive)
oai211_2AS 7t-3.3V 7,392OR-AND-Invert compound gate (2x drive)
and2_2AS 7t-3.3V 4,4162-input AND gate (2x drive)
inv_2AS 7t-3.3V 4,325Inverter (2x drive)

Logic density map

4,596 logic cells, 88,225 transistors 8,935 logic cells, 161,837 transistors 8,615 logic cells, 141,722 transistors 4,045 logic cells, 63,692 transistors 8,471 logic cells, 156,843 transistors 17,326 logic cells, 292,318 transistors 29,376 logic cells, 321,419 transistors 8,645 logic cells, 124,782 transistors 8,889 logic cells, 160,211 transistors 18,270 logic cells, 294,223 transistors 29,898 logic cells, 340,321 transistors 8,013 logic cells, 144,591 transistors 8,913 logic cells, 162,243 transistors 16,654 logic cells, 291,738 transistors 17,627 logic cells, 296,511 transistors 7,940 logic cells, 146,478 transistors 5,669 logic cells, 106,383 transistors 10,901 logic cells, 196,504 transistors 11,457 logic cells, 200,186 transistors 4,883 logic cells, 94,121 transistors 0 logic cells, 160 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors Densest SRAM-free mm²: 33,972 logic cells 5k 9k 9k 4k 8k 17k 29k 9k 9k 18k 30k 8k 9k 17k 18k 8k 6k 11k 11k 5k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (34k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. SCUP was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-12.

Every step, and the latest re-run
StepAccepted on
check 465, 2026-07-12, initial, gf180mcu-precheck 1.7.1 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 783, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.CheckPadMaskpassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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