wafer.space Run 2

SlugTPU

SCTP · Accelerators · 1 × 1 slot

Layout render of SlugTPU

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		10k (13% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		6k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		14k (19% of buffer maximum)
Core covered by logic26%
Transistor density
transistors per mm²		249k average, 228k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot A4 SCTP on the reticle
Bond pads74
Transistors3,217,831
Logic cells124,628 + 443,248 filler and tap cells
Libraries AS 7t-3.3V (125k)
SRAM17 macros, 139,264 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.5.5 or 1.5.6
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit e906c153f878.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_COMMIT 140b0494c666).
Chip-on-boardSelected at submission
PrecheckPassed the check it was accepted on, 2026-07-15, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells, ocd SRAM
Gate oxidesThin only (3.3 V) in the design itself
the pad ring adds thick-oxide (6 V) transistors
I/O librarygf180mcu_fd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

17%
13%
33%
36%
  • Logic cells 3.36 mm² (17%)
  • SRAM 2.64 mm² (13%)
  • Filler and tap cells 6.60 mm² (33%)
  • Other 0.32 mm² (2%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
xnor2_2AS 7t-3.3V 19,6582-input XNOR gate (2x drive)
dlybuff_2AS 7t-3.3V 15,896Delay buffer (2x drive)
and2_2AS 7t-3.3V 12,5852-input AND gate (2x drive)
dfxtp_2AS 7t-3.3V 10,086D flip-flop (1 bit storage, 2x drive)
maj3_2AS 7t-3.3V 9,2663-input majority gate (2x drive)
nand2_2AS 7t-3.3V 6,5882-input NAND gate (2x drive)
xor2_2AS 7t-3.3V 6,5242-input XOR gate (2x drive)
inv_2AS 7t-3.3V 4,651Inverter (2x drive)
mux2_2AS 7t-3.3V 4,0292-input multiplexer (2x drive)
ao22_2AS 7t-3.3V 3,831AND-OR compound gate (2x2 inputs, 2x drive)

Logic density map

2,411 logic cells, 50,243 transistors 7,244 logic cells, 119,061 transistors 7,485 logic cells, 122,717 transistors 1,087 logic cells, 34,478 transistors 6,944 logic cells, 116,867 transistors 11,254 logic cells, 258,072 transistors, 19% SRAM 4,553 logic cells, 310,248 transistors, 60% SRAM 6,011 logic cells, 130,050 transistors, 3% SRAM 6,859 logic cells, 120,515 transistors 8,677 logic cells, 278,595 transistors, 36% SRAM 4,380 logic cells, 304,009 transistors, 65% SRAM 6,602 logic cells, 134,787 transistors, 4% SRAM 7,330 logic cells, 128,813 transistors 11,051 logic cells, 258,021 transistors, 18% SRAM 4,732 logic cells, 310,835 transistors, 58% SRAM 6,688 logic cells, 136,106 transistors, 3% SRAM 1,794 logic cells, 49,494 transistors 9,135 logic cells, 156,850 transistors 8,642 logic cells, 151,706 transistors 1,749 logic cells, 45,534 transistors 0 logic cells, 160 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 Densest SRAM-free mm²: 14,116 logic cells 2k 7k 7k 1k 7k 11k 5k 6k 7k 9k 4k 7k 7k 11k 5k 7k 2k 9k 9k 2k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (14k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_ocd_ip_sram__sram1024x8m8wm117 8,192

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. SCTP was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-15.

Every step, and the latest re-run
StepAccepted on
check 543, 2026-07-15, initial, gf180mcu-precheck 1.7.2 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 735, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.CheckPadMaskpassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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