wafer.space Run 2

microTheia

SCMT · Other digital · 1 × 1 slot

Layout render of microTheia

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		4k (5% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		2k
over all 19.65 mm² of the slot, pad ring included
Core covered by logic7%
Transistor density
transistors per mm²		228k average

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Programmable event-based machine-vision system. Compatible with EVT2 encoded event stream delivered via SPI type-0 dedicated pins.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot B4 SCMT on the reticle
Bond pads74
Transistors2,949,999
Logic cells47,523 + 269,002 filler and tap cells
Libraries AS 7t-3.3V (48k)
SRAM41 macros, 280,576 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.5.8
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit ef69ed4d92c4.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT f6eeac7dad08).
Chip-on-boardSelected at submission
PrecheckPassed the check it was accepted on, 2026-07-15, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells, ocd SRAM
Gate oxidesThin only (3.3 V) in the design itself
the pad ring adds thick-oxide (6 V) transistors
I/O librarygf180mcu_fd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

28%
28%
36%
  • Logic cells 0.93 mm² (5%)
  • SRAM 5.58 mm² (28%)
  • Filler and tap cells 5.69 mm² (28%)
  • Other 0.71 mm² (4%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
buff_2AS 7t-3.3V 28,172Buffer (2x drive)
and2_2AS 7t-3.3V 2,5842-input AND gate (2x drive)
dfxtp_2AS 7t-3.3V 2,445D flip-flop (1 bit storage, 2x drive)
dlybuff_2AS 7t-3.3V 2,276Delay buffer (2x drive)
clkbuff_8AS 7t-3.3V 1,588Clock buffer (8x drive)
mux2_2AS 7t-3.3V 1,4382-input multiplexer (2x drive)
xnor2_2AS 7t-3.3V 1,0072-input XNOR gate (2x drive)
buff_4AS 7t-3.3V 741Buffer (4x drive)
inv_2AS 7t-3.3V 670Inverter (2x drive)
ao22_2AS 7t-3.3V 659AND-OR compound gate (2x2 inputs, 2x drive)

Logic density map

56 logic cells, 54,099 transistors, 8% SRAM 394 logic cells, 110,472 transistors, 24% SRAM 118 logic cells, 118,236 transistors, 26% SRAM 4 logic cells, 41,566 transistors, 6% SRAM 0 logic cells, 94,068 transistors, 18% SRAM 2,572 logic cells, 274,081 transistors, 59% SRAM 2,389 logic cells, 236,435 transistors, 56% SRAM 10 logic cells, 55,787 transistors, 6% SRAM 243 logic cells, 72,237 transistors, 15% SRAM 10,354 logic cells, 323,219 transistors, 54% SRAM 14,614 logic cells, 337,081 transistors, 52% SRAM 4 logic cells, 50,960 transistors, 4% SRAM 136 logic cells, 72,371 transistors, 15% SRAM 8,633 logic cells, 294,591 transistors, 55% SRAM 7,642 logic cells, 302,482 transistors, 64% SRAM 8 logic cells, 69,336 transistors, 9% SRAM 7 logic cells, 53,524 transistors, 10% SRAM 49 logic cells, 167,961 transistors, 35% SRAM 284 logic cells, 170,515 transistors, 41% SRAM 6 logic cells, 50,148 transistors, 6% SRAM 0 logic cells, 160 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 <1k <1k <1k <1k 0 3k 2k <1k <1k 10k 15k <1k <1k 9k 8k <1k <1k <1k <1k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_ocd_ip_sram__sram1024x8m8wm132 8,192
gf180mcu_ocd_ip_sram__sram256x8m8wm19 2,048

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. SCMT was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-15.

Every step, and the latest re-run
StepAccepted on
check 561, 2026-07-15, retry, gf180mcu-precheck 1.7.2 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 745, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.CheckPadMaskpassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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