wafer.space Run 2

ML-Audio SC

SCML · Accelerators · 1 × 1 slot

Layout render of ML-Audio SC

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		9k (11% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		6k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		13k (17% of buffer maximum)
Core covered by logic25%
Transistor density
transistors per mm²		278k average, 224k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Always on, low-power, general-purpose, keyword-spotting ASIC

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot D4 SCML on the reticle
Bond pads74
Transistors3,591,810
Logic cells111,492 + 303,499 filler and tap cells
Libraries AS 7t-3.3V (111k)
SRAM38 macros, 223,232 bits

Submission

Licenceproprietary declared
Repository: Apache-2.0 in LICENSE, not the declared licence
Templatewafer-space/gf180mcu-project-template 1.5.7
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 94e7733b0add.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT d658698bd8bc).
Chip-on-boardSelected at submission
PrecheckPassed the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells, ocd SRAM
Gate oxidesThin only (3.3 V) in the design itself
the pad ring adds thick-oxide (6 V) transistors
I/O librarygf180mcu_fd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

16%
23%
19%
36%
  • Logic cells 3.24 mm² (16%)
  • SRAM 4.65 mm² (23%)
  • Filler and tap cells 3.83 mm² (19%)
  • Other 1.20 mm² (6%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
buff_2AS 7t-3.3V 18,716Buffer (2x drive)
dfxtp_2AS 7t-3.3V 15,869D flip-flop (1 bit storage, 2x drive)
mux2_2AS 7t-3.3V 13,7452-input multiplexer (2x drive)
clkbuff_8AS 7t-3.3V 9,619Clock buffer (8x drive)
xnor2_2AS 7t-3.3V 7,9222-input XNOR gate (2x drive)
and2_2AS 7t-3.3V 7,7312-input AND gate (2x drive)
maj3_2AS 7t-3.3V 3,7023-input majority gate (2x drive)
nand2_2AS 7t-3.3V 3,4922-input NAND gate (2x drive)
inv_2AS 7t-3.3V 3,304Inverter (2x drive)
xor2_2AS 7t-3.3V 3,2672-input XOR gate (2x drive)

Logic density map

4,276 logic cells, 79,269 transistors, 2% SRAM 6,768 logic cells, 142,419 transistors, 6% SRAM 6,333 logic cells, 137,427 transistors, 14% SRAM 2,811 logic cells, 59,942 transistors 3,501 logic cells, 140,155 transistors, 20% SRAM 5,386 logic cells, 250,685 transistors, 52% SRAM 7,984 logic cells, 279,623 transistors, 43% SRAM 5,413 logic cells, 145,331 transistors, 10% SRAM 3,334 logic cells, 155,797 transistors, 24% SRAM 6,300 logic cells, 279,945 transistors, 48% SRAM 6,329 logic cells, 288,963 transistors, 50% SRAM 1,519 logic cells, 132,765 transistors, 30% SRAM 2,975 logic cells, 173,355 transistors, 27% SRAM 5,177 logic cells, 308,232 transistors, 54% SRAM 8,995 logic cells, 312,290 transistors, 52% SRAM 2,591 logic cells, 140,843 transistors, 28% SRAM 3,448 logic cells, 96,498 transistors, 3% SRAM 9,168 logic cells, 178,909 transistors, 6% SRAM 14,229 logic cells, 203,824 transistors, 3% SRAM 4,955 logic cells, 84,708 transistors 0 logic cells, 160 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 Densest SRAM-free mm²: 13,251 logic cells 4k 7k 6k 3k 4k 5k 8k 5k 3k 6k 6k 2k 3k 5k 9k 3k 3k 9k 14k 5k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (13k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_ocd_ip_sram__sram1024x8m8wm123 8,192
gf180mcu_ocd_ip_sram__sram256x8m8wm113 2,048
gf180mcu_ocd_ip_sram__sram512x8m8wm12 4,096

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. SCML was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-14.

Every step, and the latest re-run
StepAccepted on
check 526, 2026-07-14, initial, gf180mcu-precheck 1.7.2 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 723, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.CheckPadMaskpassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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