Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 15k
(20% of buffer maximum) over the 4.46 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 7k
over all 9.57 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 27k (35% of buffer maximum) |
| Core covered by logic | 33% |
| Transistor density transistors per mm² | 236k average, 263k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Dual Core BIO: The Bao I/O Co-processor from baochip-1x with 4Kb of SRAM on gf180 with SPI host.
| Die | 1.94 × 5.12 mm (9.9 mm²) |
|---|---|
| Core area | 4.46 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 9.57 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot G3 |
| Bond pads | 72 |
| Transistors | 1,052,339 |
| Logic cells | 66,232 + 120,983 filler and tap cells |
| Libraries | 7t-5V (66k) |
| SRAM | 8 macros, 32,768 bits |
Submission
| Licence | CERN-OHL-P-2.0 declared
Repository: CERN-OHL-W-2.0 in LICENSE, not the declared licence |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.5.7 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 0fe3252bd4af.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT d658698bd8bc). |
| Chip-on-board | Selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.1 (from its image)
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells, fd SRAM |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| I/O library | gf180mcu_fd_io (850 cells) |
Where the area went
How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.
- Logic cells 1.46 mm² (15%)
- SRAM 1.68 mm² (17%)
- Filler and tap cells 1.22 mm² (12%)
- Other 0.09 mm² (1%)
- Pad ring 5.47 mm² (55%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| nand2_1 | 7t-5V | 20,040 | 2-input NAND gate |
| oai21_1 | 7t-5V | 5,522 | OR-AND-Invert compound gate |
| clkinv_1 | 7t-5V | 5,316 | Clock inverter |
| nand3_1 | 7t-5V | 5,240 | 3-input NAND gate |
| dffq_1 | 7t-5V | 3,634 | D flip-flop (1 bit storage) |
| dlyc_1 | 7t-5V | 3,251 | Delay buffer |
| buf_4 | 7t-5V | 2,285 | Buffer (4x drive) |
| inv_1 | 7t-5V | 2,229 | Inverter |
| aoi21_1 | 7t-5V | 2,133 | AND-OR-Invert compound gate |
| nor2_1 | 7t-5V | 2,015 | 2-input NOR gate |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (27k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_fd_ip_sram__sram512x8m8wm1 | 8 | 4,096 |
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. DPK1 was accepted on this check, and has been checked again since with newer rules.
All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-14.
Every step, and the latest re-run
| Step | Accepted on check 484, 2026-07-14, initial, gf180mcu-precheck 1.7.1 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 | Latest re-run check 789, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.CheckPadMask | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.