Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
122 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Test chip for the 3.3V SRAM macros (256 byte, 512 byte, and 1kbyte) from the library gf180mcu_ocd_ip_sram.
The test chip consists of one each of the 1kB and 512B SRAM cores and two 256B cores pinned out to individual GPIO pins.
Also there is a POR macro with a test output.
Source repository Bonding results
| Die | 3.93 × 2.53 mm (9.9 mm²) |
|---|---|
| Core area | 5.01 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 9.61 mm² (the die less its 26 µm seal ring) |
| Placements | 2 on the reticle, in slots B1, C1 |
| Bond pads | 72 |
| Transistors | 168,624 |
| Logic cells | 122 + 445 filler and tap cells |
| Libraries | AS 7t-3.3V (120), 7t-5V (2) |
| SRAM | 4 macros, 16,384 bits |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 (in source file headers) — agrees |
|---|---|
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 6d4f6099546c. |
| Chip-on-board | Not selected at submission · bonding results |
| Precheck | Passed
the check it was accepted on, 2026-01-02, gf180mcu-precheck 1.5.5 (from its image)
step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | AS 7t-3.3V standard cells, ocd SRAM |
|---|---|
| 5 V | 7t-5V standard cells, 44 custom transistors |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MIM capacitors | 9
(900 µm², between Metal4 and Metal5)
all in reused simple_por |
| High-resistance poly resistors | 88
(2,200 µm²)
all in reused simple_por |
| I/O library | gf180mcu_ocd_io (758 cells) |
Where the area went
How this design's area splits between logic cells, SRAM, other and pad ring.
- Logic cells 0.01 mm² (<1%)
- SRAM 0.39 mm² (4%)
- Other 4.62 mm² (46%)
- Pad ring 4.93 mm² (50%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| buff_12 | AS 7t-3.3V | 104 | Buffer (12x drive) |
| mux2_4 | AS 7t-3.3V | 16 | 2-input multiplexer (4x drive) |
| inv_12 | 7t-5V | 1 | Inverter (12x drive) |
| inv_8 | 7t-5V | 1 | Inverter (8x drive) |
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_ocd_ip_sram__sram1024x8m8wm1 | 1 | 8,192 |
| gf180mcu_ocd_ip_sram__sram256x8m8wm1 | 2 | 2,048 |
| gf180mcu_ocd_ip_sram__sram512x8m8wm1 | 1 | 4,096 |
How this design grew
ocd_sram_test has been made on 2 shuttles since Dec 2025. Every version, oldest first, with this one in bold:
- Dec 2025 · wafer.space Run 1 OCD2 ocd_sram_test — 1 × ½ slot
- Jul 2026 · wafer.space Run 2 OCD3 3.3V SRAM test 2 — 1 × ½ slot
Tiny Tapeout tile Google shuttle wafer.space die
Its dies compared
Every die of this design measured here, oldest first, with this one in bold.
| Made on | Slot | Library | Gate oxides | Logic cells | Per mm² of core | Densest | SRAM |
|---|---|---|---|---|---|---|---|
| wafer.space Run 1 · OCD2 | 1 × ½ | mixed | 3.3 V and 5 V/6 V | 122 | — | — | 4 macros |
| wafer.space Run 2 · OCD3 | 1 × ½ | AS 7t-3.3V | 3.3 V only | 123 | — | — | 4 macros |
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. OCD2 was accepted on this check.
All 15 steps passed, with 0 KLayout DRC errors, on 2026-01-02.
Every step
| Step | Accepted on, and latest check 209, 2026-01-02, initial, gf180mcu-precheck 1.5.5 (from its image) PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e |
|---|---|
| KLayout.ReadLayout | passed |
| KLayout.CheckTopLevel | passed |
| KLayout.CheckSize | passed |
| KLayout.GenerateID | passed |
| KLayout.Density | passed |
| Checker.KLayoutDensity | passed |
| KLayout.ZeroAreaPolygons | passed |
| Checker.KLayoutZeroAreaPolygons | passed |
| KLayout.Antenna | passed |
| Checker.KLayoutAntenna | passed |
| Magic.DRC | passed |
| Checker.MagicDRC | passed |
| KLayout.DRC | passed |
| Checker.KLayoutDRC | passed |
| KLayout.WriteLayout | passed |
| KLayout DRC errors | 0 |
| Magic DRC errors (advisory) | 0 |
| Files | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.