wafer.space Run 1

openframe_caravel_picorv32

OCD1 · RISC-V and CPUs · 1 × 1 slot

Layout render of openframe_caravel_picorv32

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		3k (4% of buffer maximum)
over the 12.90 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		2k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		10k (14% of buffer maximum)
Core covered by logic7%
Transistor density
transistors per mm²		117k average, 189k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Synthesis test of the gf180mcu_ocd_io, gf180mcu_ocd_ip_sram, and gf180mcu_as_sc_mcu7t3v3 libraries with a project framework similar to the Efabless "openframe" version of Caravel for sky130.

Source repository Die photograph

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot E2 OCD1 on the reticle
Bond pads63
Transistors1,515,877
Logic cells34,431 + 524,019 filler and tap cells
Libraries AS 7t-3.3V (34k), 7t-5V (2)
SRAM8 macros, 24,576 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 (in source file headers) — agrees
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 9ef4567172df.
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2026-01-02, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells, ocd SRAM
5 V7t-5V standard cells
6 V44 custom transistors
Gate oxidesThin (3.3 V) and thick (5 V/6 V) in the design itself
MIM capacitors9 (900 µm², between Metal4 and Metal5)
all in reused simple_por
High-resistance poly resistors88 (2,200 µm²)
all in reused simple_por
I/O librarygf180mcu_ocd_io (1102 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells and pad ring.

57%
35%
  • Logic cells 0.96 mm² (5%)
  • SRAM 0.66 mm² (3%)
  • Filler and tap cells 11.83 mm² (57%)
  • Pad ring 7.22 mm² (35%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
inv_2AS 7t-3.3V 5,088Inverter (2x drive)
mux2_2AS 7t-3.3V 4,6692-input multiplexer (2x drive)
buff_2AS 7t-3.3V 3,598Buffer (2x drive)
dfxtp_2AS 7t-3.3V 3,452D flip-flop (1 bit storage, 2x drive)
buff_8AS 7t-3.3V 2,472Buffer (8x drive)
and2_2AS 7t-3.3V 1,7012-input AND gate (2x drive)
ao22_2AS 7t-3.3V 1,593AND-OR compound gate (2x2 inputs, 2x drive)
clkbuff_12AS 7t-3.3V 1,307Clock buffer (12x drive)
dfsrtp_2AS 7t-3.3V 1,194D flip-flop with set and reset (2x drive)
or2_2AS 7t-3.3V 1,1742-input OR gate (2x drive)

Logic density map

159 logic cells, 28,830 transistors 1,791 logic cells, 68,696 transistors 787 logic cells, 66,286 transistors, 7% SRAM 146 logic cells, 27,279 transistors 287 logic cells, 46,661 transistors 3,819 logic cells, 113,737 transistors 6,633 logic cells, 170,936 transistors, 14% SRAM 1,398 logic cells, 56,225 transistors 515 logic cells, 49,149 transistors 5,830 logic cells, 136,367 transistors 6,768 logic cells, 182,811 transistors, 16% SRAM 286 logic cells, 42,136 transistors 775 logic cells, 52,966 transistors 1,866 logic cells, 88,007 transistors 1,077 logic cells, 128,057 transistors, 19% SRAM 842 logic cells, 49,747 transistors 113 logic cells, 34,256 transistors 511 logic cells, 56,824 transistors 648 logic cells, 83,989 transistors, 10% SRAM 180 logic cells, 32,067 transistors 0 logic cells, 178 transistors 0 logic cells, 252 transistors 0 logic cells, 258 transistors 0 logic cells, 163 transistors gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 gf180mcu_ocd_ip_sram__sram256x8m8wm1 Densest SRAM-free mm²: 10,353 logic cells <1k 2k 1k <1k <1k 4k 7k 1k 1k 6k 7k <1k 1k 2k 1k 1k <1k 1k 1k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (10k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_ocd_ip_sram__sram256x8m8wm14 2,048
gf180mcu_ocd_ip_sram__sram512x8m8wm14 4,096

The fabricated die

A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0

Die photograph of openframe_caravel_picorv32 by InfoSecDJ

InfoSecDJ's zoomable viewer · Larger image · full resolution (very large file) · all photographs

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. OCD1 was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2026-01-02.

Every step, and the latest re-run
StepAccepted on
check 214, 2026-01-02, initial, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e		Latest re-run
check 730, 2026-08-02, retry, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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