Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
123 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
A variant of the 3.3V SRAM test chip submitted for the first shuttle run.
This one has the new 64 byte SRAM block on it, which was designed to (maybe) fit in a single Tiny Tapeout tile.
It also has a new design of a 3.3V power-on-reset (PoR) block.
| Die | 3.93 × 2.53 mm (9.9 mm²) |
|---|---|
| Core area | 5.01 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 9.61 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot C2 |
| Bond pads | 72 |
| Transistors | 158,397 |
| Logic cells | 123 + 442 filler and tap cells |
| Libraries | AS 7t-3.3V (123) |
| SRAM | 4 macros, 14,848 bits |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 (in source file headers) — agrees |
|---|---|
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 6d4f6099546c. |
| Chip-on-board | Selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-04
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | AS 7t-3.3V standard cells, ocd SRAM, 177 custom transistors |
|---|---|
| Gate oxides | Thin only (3.3 V) in the design itself the pad ring adds thick-oxide (5 V, 6 V) transistors |
| MIM capacitors | 40 (4,000 µm², between Metal4 and Metal5) |
| High-resistance poly resistors | 200 (5,000 µm²) |
| Diodes | 1 (0 µm²) |
| I/O library | gf180mcu_ocd_io (758 cells) |
Where the area went
How this design's area splits between logic cells, SRAM, other and pad ring.
- Logic cells 0.01 mm² (<1%)
- SRAM 0.37 mm² (4%)
- Other 4.64 mm² (47%)
- Pad ring 4.93 mm² (50%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| buff_12 | AS 7t-3.3V | 106 | Buffer (12x drive) |
| mux2_4 | AS 7t-3.3V | 16 | 2-input multiplexer (4x drive) |
| inv_4 | AS 7t-3.3V | 1 | Inverter (4x drive) |
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_ocd_ip_sram__sram1024x8m8wm1 | 1 | 8,192 |
| gf180mcu_ocd_ip_sram__sram256x8m8wm1 | 1 | 2,048 |
| gf180mcu_ocd_ip_sram__sram512x8m8wm1 | 1 | 4,096 |
| gf180mcu_ocd_ip_sram__sram64x8m8wm1 | 1 | 512 |
How this design grew
3.3V SRAM test 2 has been made on 2 shuttles since Dec 2025. Every version, oldest first, with this one in bold:
- Dec 2025 · wafer.space Run 1 OCD2 ocd_sram_test — 1 × ½ slot
- Jul 2026 · wafer.space Run 2 OCD3 3.3V SRAM test 2 — 1 × ½ slot
Tiny Tapeout tile Google shuttle wafer.space die
Its dies compared
Every die of this design measured here, oldest first, with this one in bold.
| Made on | Slot | Library | Gate oxides | Logic cells | Per mm² of core | Densest | SRAM |
|---|---|---|---|---|---|---|---|
| wafer.space Run 1 · OCD2 | 1 × ½ | mixed | 3.3 V and 5 V/6 V | 122 | — | — | 4 macros |
| wafer.space Run 2 · OCD3 | 1 × ½ | AS 7t-3.3V | 3.3 V only | 123 | — | — | 4 macros |
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. OCD3 was accepted on this check, and has been checked again since with newer rules.
All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-04.
Every step, and the latest re-run
| Step | Accepted on check 342, 2026-07-04, initial | Latest re-run check 747, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.CheckPadMask | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.