Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 5k
(9% of buffer maximum) over the 12.92 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 4k
over all 19.65 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 14k (23% of buffer maximum) |
| Core covered by logic | 23% |
| Transistor density transistors per mm² | 184k average, 216k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
A video games console on a chip. RISC-V CPU, RISC-V APU and custom graphics hardware.
Source repository Die photograph
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 12.92 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 19.65 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot G2 |
| Bond pads | 74 |
| Transistors | 2,380,904 |
| Logic cells | 69,949 + 179,358 filler and tap cells |
| Libraries | 9t-5V (70k) |
| SRAM | 30 macros, 118,784 bits |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.3.1 or 1.3.2 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 8c2bfda6461c.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.4). |
| Chip-on-board | Not selected at submission |
| Precheck | No finished precheck recorded |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 9t-5V standard cells, fd SRAM |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| I/O library | gf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells) |
Where the area went
How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.
- Logic cells 2.93 mm² (15%)
- SRAM 6.16 mm² (31%)
- Filler and tap cells 3.19 mm² (16%)
- Other 0.64 mm² (3%)
- Pad ring 7.20 mm² (36%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| nand2_1 | 9t-5V | 17,153 | 2-input NAND gate |
| clkinv_1 | 9t-5V | 5,513 | Clock inverter |
| nor2_1 | 9t-5V | 5,029 | 2-input NOR gate |
| nand3_1 | 9t-5V | 3,187 | 3-input NAND gate |
| oai21_4 | 9t-5V | 2,868 | OR-AND-Invert compound gate (4x drive) |
| nand2_2 | 9t-5V | 2,828 | 2-input NAND gate (2x drive) |
| nand2_4 | 9t-5V | 2,765 | 2-input NAND gate (4x drive) |
| sdffq_4 | 9t-5V | 2,132 | Scan D flip-flop (4x drive) |
| sdffrnq_4 | 9t-5V | 2,110 | Scan D flip-flop with reset (4x drive) |
| sdffq_1 | 9t-5V | 1,954 | Scan D flip-flop |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (14k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_fd_ip_sram__sram256x8m8wm1 | 2 | 2,048 |
| gf180mcu_fd_ip_sram__sram512x8m8wm1 | 28 | 4,096 |
The fabricated die
A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0
