wafer.space Run 2

Cloneless2

CLON · Security · 1 × 1 slot

Layout render of Cloneless2

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		25k (33% of buffer maximum)
over the 12.90 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		16k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		30k (39% of buffer maximum)
Core covered by logic58%
Transistor density
transistors per mm²		283k average, 290k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Cloneless2 is the second tapeout in the Cloneless series of tamper-resistant open-source ASICs.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot B5 CLON on the reticle
Bond pads32
Transistors3,653,694
Logic cells323,612 + 486,920 filler and tap cells
Libraries 7t-5V (324k)
SRAMNo SRAM

Submission

LicenceGPL-3.0-only declared
Repository: GPL-3.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.5.7
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit a63883b6fa7b.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT d658698bd8bc).
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2026-07-13, gf180mcu-precheck 1.7.1 (from its image)
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (1390 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and pad ring.

37%
26%
36%
  • Logic cells 7.42 mm² (37%)
  • Filler and tap cells 5.22 mm² (26%)
  • Other 0.26 mm² (1%)
  • Pad ring 7.22 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 54,1772-input NAND gate
xor2_17t-5V 50,9252-input XOR gate
nor2_17t-5V 28,5642-input NOR gate
clkinv_17t-5V 20,071Clock inverter
aoi21_17t-5V 19,991AND-OR-Invert compound gate
oai21_17t-5V 19,489OR-AND-Invert compound gate
xnor2_17t-5V 18,9112-input XNOR gate
dlyb_17t-5V 17,393Delay buffer
dffq_17t-5V 12,101D flip-flop (1 bit storage)
and2_17t-5V 9,4082-input AND gate

Logic density map

869 logic cells, 75,632 transistors 14,704 logic cells, 159,671 transistors 15,084 logic cells, 156,356 transistors 2,630 logic cells, 69,246 transistors 13,149 logic cells, 152,818 transistors 28,266 logic cells, 280,681 transistors 29,567 logic cells, 288,255 transistors 8,811 logic cells, 129,540 transistors 14,146 logic cells, 151,286 transistors 28,781 logic cells, 298,343 transistors 27,315 logic cells, 285,569 transistors 13,648 logic cells, 143,054 transistors 13,741 logic cells, 152,960 transistors 28,079 logic cells, 283,732 transistors 28,960 logic cells, 295,260 transistors 13,401 logic cells, 140,628 transistors 6,962 logic cells, 102,144 transistors 16,645 logic cells, 204,672 transistors 13,281 logic cells, 194,187 transistors 5,573 logic cells, 88,705 transistors 0 logic cells, 194 transistors 0 logic cells, 292 transistors 0 logic cells, 292 transistors 0 logic cells, 177 transistors Densest SRAM-free mm²: 29,930 logic cells 1k 15k 15k 3k 13k 28k 30k 9k 14k 29k 27k 14k 14k 28k 29k 13k 7k 17k 13k 6k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (30k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. CLON was accepted on this check, and has been checked again since with newer rules.

All 16 steps passed, with 0 KLayout DRC errors, on 2026-07-13.

Every step, and the latest re-run
StepAccepted on
check 479, 2026-07-13, initial, gf180mcu-precheck 1.7.1 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 784, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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