Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 1k
(1% of buffer maximum) over the 4.47 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | <1k
over all 9.57 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 2k (2% of buffer maximum) |
| Core covered by logic | 2% |
| Transistor density transistors per mm² | 245k average, 215k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
| Die | 1.94 × 5.12 mm (9.9 mm²) |
|---|---|
| Core area | 4.47 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 9.57 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot G5 |
| Bond pads | 72 |
| Transistors | 1,094,448 |
| Logic cells | 3,788 + 78,222 filler and tap cells |
| Libraries | 7t-5V (4k) |
| SRAM | No SRAM |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 (in source file headers) — agrees |
|---|---|
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 2ce18dbe27df. |
| Chip-on-board | Selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-15, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells, 323,352 custom transistors |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| I/O library | gf180mcu_fd_io (850 cells) |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and pad ring.
- Logic cells 0.08 mm² (1%)
- Filler and tap cells 3.21 mm² (32%)
- Other 1.18 mm² (12%)
- Pad ring 5.46 mm² (55%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| buf_2 | 7t-5V | 1,246 | Buffer (2x drive) |
| buf_4 | 7t-5V | 1,230 | Buffer (4x drive) |
| buf_1 | 7t-5V | 788 | Buffer |
| clkbuf_1 | 7t-5V | 300 | Clock buffer |
| aoi22_1 | 7t-5V | 66 | AND-OR-Invert (2x2 inputs) |
| dffq_1 | 7t-5V | 37 | D flip-flop (1 bit storage) |
| clkbuf_2 | 7t-5V | 34 | Clock buffer (2x drive) |
| dffq_2 | 7t-5V | 24 | D flip-flop (1 bit storage, 2x drive) |
| nand3_2 | 7t-5V | 9 | 3-input NAND gate (2x drive) |
| and4_1 | 7t-5V | 8 | 4-input AND gate |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (2k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. FS03 was accepted on this check, and has been checked again since with newer rules.
All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-15.
Every step, and the latest re-run
| Step | Accepted on check 664, 2026-07-15, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 | Latest re-run check 777, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.CheckPadMask | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | advisory warning | advisory warning |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 1,260 | 1,260 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.