Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 16k
(21% of buffer maximum) over the 12.92 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 10k
over all 19.65 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 27k (36% of buffer maximum) |
| Core covered by logic | 49% |
| Transistor density transistors per mm² | 264k average, 300k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
An open source FPGA generated using the FABulous eFPGA framework that can be programmed using Yosys and nextpnr. It can be configured via an active or passive SPI interface. In active mode, the bitstream is read from an external SPI flash from one of 16 slots. Specs: 48x I/Os, 480x LUT4, 6x SRAM 512x8, 6x MAC, 12x Register file
Source repository Die photograph
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 12.92 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 19.65 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot E3 |
| Bond pads | 74 |
| Transistors | 3,404,438 |
| Logic cells | 203,757 + 295,366 filler and tap cells |
| Libraries | 7t-5V (204k) |
| SRAM | 6 macros, 24,576 bits |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.3.5 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 97da81d42c9e.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.6). |
| Chip-on-board | Not selected at submission |
| Precheck | Passed
the check it was accepted on, 2025-12-16, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells, fd SRAM |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| I/O library | gf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells) |
Where the area went
How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.
- Logic cells 6.37 mm² (32%)
- SRAM 1.26 mm² (6%)
- Filler and tap cells 4.52 mm² (22%)
- Other 0.77 mm² (4%)
- Pad ring 7.20 mm² (36%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| latq_1 | 7t-5V | 51,691 | Latch (level-sensitive) |
| buf_1 | 7t-5V | 44,562 | Buffer |
| mux4_1 | 7t-5V | 24,574 | 4-input multiplexer |
| nand2_1 | 7t-5V | 12,165 | 2-input NAND gate |
| clkinv_1 | 7t-5V | 11,068 | Clock inverter |
| mux2_2 | 7t-5V | 8,107 | 2-input multiplexer (2x drive) |
| nor2_1 | 7t-5V | 7,689 | 2-input NOR gate |
| oai21_1 | 7t-5V | 6,855 | OR-AND-Invert compound gate |
| aoi21_1 | 7t-5V | 6,256 | AND-OR-Invert compound gate |
| oai211_1 | 7t-5V | 3,436 | OR-AND-Invert compound gate |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (27k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_fd_ip_sram__sram512x8m8wm1 | 6 | 4,096 |
How this design grew
FABulous FPGA has been made on 9 shuttles since Dec 2022. Every version, oldest first, with this one in bold:
- Dec 2022 · Google GFMPW-0 56C6 One-hot FABulous FPGA — Caravel chip, a one-hot FPGA built with the FABulous framework
- Dec 2025 · wafer.space Run 1 MOLE FABulous FPGA — 1 × 1 slot
- Mar 2026 · Tiny Tapeout IHP 26a Tiny FABulous FPGA — 8 × 4 tiles
- May 2026 · Tiny Tapeout SKY 26a Tiny FABulous FPGA — 8 × 4 tiles
- May 2026 · Tiny Tapeout SKY 26b Tiny FABulous FPGA — 8 × 4 tiles
- Jun 2026 · Tiny Tapeout GF 0.3 Tiny FABulous FPGA — 4 × 4 tiles Tiny FABulous FPGA (3.3V version) — 4 × 4 tiles, 3.3 V version
- Jul 2026 · wafer.space Run 2 MOLE FABulous FPGA — 1 × 1 slot
- Sep 2026 · Tiny Tapeout SKY 26c Tiny FABulous FPGA — 8 × 4 tiles
- Sep 2026 · Tiny Tapeout IHP 26b Tiny FABulous FPGA — 6 × 4 tiles
Tiny Tapeout tile Google shuttle wafer.space die
Its dies compared
Every die of this design measured here, oldest first, with this one in bold.
| Made on | Slot | Library | Gate oxides | Logic cells | Per mm² of core | Densest | SRAM |
|---|---|---|---|---|---|---|---|
| Google GFMPW-0 · 56C6 | 1 × 1 | 7t-5V | 5 V/6 V only | 32,037 | 4k | 5k | none |
| wafer.space Run 1 · MOLE | 1 × 1 | 7t-5V | 5 V/6 V only | 203,757 | 16k | 27k | 6 macros |
| wafer.space Run 2 · MOLE | 1 × 1 | AS 7t-3.3V | 3.3 V only | 211,813 | 16k | 24k | 13 macros |
Parts of this design are on Tiny Tapeout chips too
Tiny Tapeout puts many small designs on one chip, so trying out a block costs a fraction of a whole die: a cheap way to test one piece of a bigger design before it goes on a die of its own.
The fabricated die
A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. MOLE was accepted on this check, and has been checked again since with newer rules.
All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-16.
Every step, and the latest re-run
| Step | Accepted on check 115, 2025-12-16, initial, gf180mcu-precheck 1.5.5 (from its image) PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e | Latest re-run check 753, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | not in this flow | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.